Design Engineering

DIVYA YOGINDER KUMAR

+1-607-***-**** ac8150@r.postjobfree.com

https://www.linkedin.com/in/divya-yoginder-0aa1a4149 Authorized to work in the U.S (currently on F1- OPT)

EDUCATIONAL QUALIFICATION:

Master of Science in Electrical and Computer Engineering, State University Of New York at Binghamton GPA-3.36/4 Fall 2018.

Bachelor of Engineering in Electronics and Communication Engineering, Anna University GPA-8.71/10 Spring 2015.

SKILLS:

EDA tools: Cadence Virtuoso, Synopsys, SPICE Simulator. OrCAD

Programming languages: Verilog, System Verilog, C/C++, VHDL, Embedded C, SQL, Python, TCL. UVM Basics

Simulation and Design tools: Xilinx, MATLAB, ModelSIM PE, Quartus II, LabVIEW, Altera (Quartus Prime), AutoCAD Electrical, PLL.

Operating system & Databases: Windows (All versions), IOS, Unix/Linux and MySQL. Mentor graphics

Courses: VLSI Design, Digital system design, SOC Design, Power Electronics, CMOS Design, Microfabrication, Digital Communication, Wireless Communication, Embedded Systems, Neural Networks and Deep learning.

WORK EXPERIENCE:

Programmer Analyst, Cognizant. Ltd, Chennai, India Mar 2015 – Nov 2016

Effectively developed, debugged and tested structural program modules of databases according to Client needs for a Fortune 500 company.. Performed test bench design and implementation and involved in test plans.

Improved product delivery time by 15% by helping fix a major design issue using C/C++, VSAM, JCL, Python, DB and OOPS Cconcepts.

Developed team building and responsibility in handling crucial issues presented by the customer.

Electrical Engineering Intern, Bharat Sanchar Nigam Limited (BSNL), Chennai, India May 2014 - Aug 2014

Engineered a Variable Duty Cycle PWM signal generator using FPGA with 10% improved power output. Xilinx ISE and Spartan 6 FPGA were utilized.

Gained hands-on experience in GSM and LTE Cellular Network Design and gained the working experience in Base Station and Mobile Switching Centre.

ACADEMIC PROJECTS:

Data path design, Control path design and Verification of a 16-bit MIPS Processor (Verilog)- Spring 2018

Reviewed and simulated a Verilog model of the processor. Designed data path by assembling and connecting word slices into an ALU. RTL coding and verification was performed.

Used Synopsys’s Design Compiler to synthesize the combinational logic for the control FSM. Both Cadence and Synopsys were used in the project.

Design and Verification of 5-Stage pipelined 32-bit floating point multiplier (Verilog)- Fall 2017

Development of a hardware software co-design system to multiply single precision 32 - bit floating point binary numbers with reduced delay, according to IEEE 754-1985, standard. Using the Xilinx ISE and EDK. Executed on a Spartan 6 FPGA

Hardware/Software communication architecture in a RISC processor (System C)- Fall 2017

Design of an effective communication pathway between the single master-multi slave protocol in a RISC processor.

System-C was used as a communication tool between the hardware systems gaining insight in the computer architecture.

Design and Development of Multi-Directional Unmanned ground vehicle (Embedded C)- Spring 2015

Developed a 16-bit PIC controller based UGV with a ZigBee module, programmed and complied it using embedded C in Microsoft Visual studio and Keil compiler.

Vision Based Driver Assistance at night using PIC controller (Embedded C) - Fall 2015

Implemented in automobiles for dimming the light and control the speed to follow a forward vehicle during night.

PIC controller and ambient light sensors were used to detect the speed and distance of the object. ARM

HONORS AND AWARDS:

Awarded the prestigious Prime Minister Scholarship India for excellence in academics from 2011 to 2014.

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