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Engineer Developer

Location:
Katy, Texas, United States
Salary:
59000
Posted:
December 16, 2018

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Resume:

SHWETHA GURUNATH

***** **** ****** ****, ****, TX-77494. Ph No: 281-***-****, Email: ac7zfo@r.postjobfree.com

LinkedIn: https://www.linkedin.com/in/shwetha-gurunath-290129106

Objective: Seeking to obtain Hardware engineer position that will utilize my skills and knowledge in electrical engineering and circuit design.

Education:

Master of Science in Electrical and Computer Engineering, University of Houston G.P.A:3.266 (Class of 2018)

Coursework: Advanced Digital Design, Advanced Hardware Design, Advanced VLSI, Advanced VLSI (Rice University), Advanced Computer Architecture, Microlithography and Optical Fiber Communication.

Bachelor of Science in Electronics and Communication Engineering, VTU (India) G.P.A:3.482 (Class of 2015)

Technical Skills:

Proficient with Verilog, VHDL, System Verilog, MATLAB and C programming.

Proficient in: Altera Quartus, ModelSim, Cadence Virtuoso, Xilinx, VivadoHLS and Silvaco.

Proficient in C, C++, R, Python and Linux.

Good practical knowledge in circuit designing and simulation of IC’s, CMOS, BJT’s using Cadence Virtuoso and SILVACO. Presently pursuing Altium Designer Course.

SoC Integration using VivadoHLS and Xilinx.

Work Experience:

Developer, NTT DATA Global Services, Bangalore, India, December 2015 – July 2016

Worked as a developer as a part to develop applications using C++ and C programming.

Involved in Maintenance of the application.

Intern, Pepperl FUCHS PVT LTD, Bangalore, India, January 2014 – February 2014

Worked on calibration of Zener and Barrier Diodes that are implemented in Hazardous Regions for safety measures.

A part of the testing team to detect and correct the faulty diodes.

Academic Projects:

Whack-a-Mole using FPGA board Languages/Tools Used: Verilog, Altera Quartus, Modelsim, FPGA Board.

Emulated Whack-a-Mole game on FPGA using Altera Quartus and Modelsim with synthesized timer, random number generator, LFSR, ROM based password authentication and RAM based scoring system.

Hardware-based True Random Number Generator & ROM-based Game Access Control on FPGA Languages/Tools Used: Verilog, Altera Quartus, Modelsim, FPGA Board

Scrambled Numbering Game where a random number is generated on one display and the player enters the scrambled number such that the sum of the random number and the unscrambled input is 15.

SoC Integration of QRD Array Languages/Tools Used: C++, Matlab, ARM Core

Solved 4x4 Linear System with ARM Core and CORDIC QRD and Matrix-Multiplication Accelerator

Integration. Explored the integration of a programmable processing core with a custom accelerator in the context of Vivado through Xilinx Platform Studio (Xilinx SDK) and Xilinx System Generator.

HealthyHeart Languages/Tools Used: C, Rasberry Pi

The project involved integrating hardware and software aspects of developing a standalone product. Hardware used was Raspberry Pi and software involved using cloud database. A product that keeps track of the heart health was developed.

Remote Monitoring and Billing System For Electric Energy Using ARM Processor Languages/Tools Used: C, ARM

Study carried out by developing a remote monitoring system for the energy consumed for domestic purpose. It involved the use of GSM modules and ARM processor for the implementation of the same.

Door Bell Assistance for Deaf With Smoke And LPG Languages/Tools Used: C, ARM

A product that detects Smoke and LPG leak and notify with an alarm.



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