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Engineer Design

Location:
Manchester, New Hampshire, United States
Posted:
December 09, 2018

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Resume:

DOUGLAS W. BABCOCK

*** ***** ****

Manchester, NH 03109

603-***-****

Email: ac7wwo@r.postjobfree.com

Chief Hardware Engineer, Analog Integrated Circuit Design

An IC design engineering professional with over thirty years of diversified electronic experience, who specializes in the group management and design of leading edge, mixed signal CMOS and Bipolar Integrated Circuits.

Present Experience

National Instruments, Inc. Austin, TX (work remote in Manchester, NH)

Chief Hardware Engineer May 2018 – Present

Principal Hardware Engineer March 2008 – May 2018

Design Engineering Consultant October 2007 – March 2008

Design and implementation of various SMU Sigma Delta Modulator IC’s in 0.35 uM CMOS process

Design and implementation of 2.5 GSPS Time-to-Digital Converter IC in 60 GHz SiGe HBT process

Design of very low noise CMOS op-amp family in 0.35 uM CMOS

Designs included various bandgap, ADC/DAC, comparator, regulator and other analog cells

First NI employee hired for captive, in-house analog IC design service

Prime orchestrator of external foundry IC development methodology

First company adopter of Cadence EDA tools (Virtuoso schematic, layout, ADE, Assura)

Consultant to corporate ASIC development strategy

Consultant to corporate counsel on IP issues.

Additional Experience

Analog Devices, Inc. Wilmington, MA

Manager, Advanced Development, IC Design Engineering Group 2004 – March 2008

Directed the conception, design and layout of state-of-the-art circuits utilized in integrated circuits for the Automatic Test Equipment industry.

Circuits consist generally of Pin Drivers, Comparators, Active Loads, ADC/DAC and PMU’s as well as peripheral logic and high frequency passive matching networks.

Group utilizes high speed complimentary Bipolar and BiCMOS semiconductor processes.

Overall team consists of 15 design, manufacturing, test and process engineers.

Managed group budget of >$10 million.

Achieved group operating profit before taxes (OPBT) >30%.

Division and senior staff member consulting on technical issues relating to process and industry.

Consultant to corporate advanced process development.

Consultant to corporate counsel on IP issues.

Chairman of division innovation team responsible for assisting in the review of potential IP.

10 patents issued to design group in FY05.

Analog Devices, Inc. Wilmington, MA

Manager, IC Design Engineering Group 1995 – 2004

Directed the design and layout of state-of-the-art platform Pin Electronics integrated circuits for the Automatic Test Equipment industry.

Design wins in all major ATE companies worldwide.

Senior division staff member for $100+ million product line.

Managed group budget of >$20 million.

Group consisted of 30 design, process and test engineers.

Within 5 years, products established ADI in dominant position as world’s number one OEM Pin Electronics IC supplier with 60% OEM market share.

Played key role in development and evolution of three major complimentary bipolar semiconductor processes.

Group designed and released to market over 60 products.

Over 50 patents issued to design group.

Analog Devices, Inc. Wilmington, MA

Senior Staff Design Engineer, ATE Pin Electronics 1992 – 1995

Designed what is still today, the most accurate, highest fidelity Pin Driver in the world (2 patents).

Design lead on numerous monolithic Driver/Comparator/Loads (DCL’s).

Corporate resource for interdivisional design reviews and interviews.

Co-design of ATE timing vernier delay locked loop and current mode loop correction distribution scheme.

Cadence EDA tools

Analog Devices, Inc. Wilmington, MA

Staff Design Engineer, ATE Pin Electronics 1988 – 1992

Design of world’s first monolithic high speed Active Load for ATE industry (patented).

Design of world’s first high voltage, high speed, low dispersion comparator for ATE industry.

Design of world’s first monolithic Pin Driver with high voltage test mode.

Co-design of world’s first monolithic DCL.

Two designs used for first verification of corporation’s first two DI/SOI CB processes.

Patents

7470968 T-Coil Apparatus and Method for Compensating Capacitance

7248035 Automatic Test Equipment Pin Channel with T-Coil Compensation

6737857 Apparatus and Method for Driving Circuit Pins in a Circuit Testing System

6677775 Circuit Testing Device Using a Driver to Perform Electronics Testing

5434446 Parasitic Capacitance Cancellation Circuit

5424510 Circuit and Method of Providing Thermal Compensation for Transistor …

5010297 Automatic Test Equipment with Active Load having High-Speed Inhibit Mode Switching

Education

University of Lowell, BSEE, GPA 3.4/4.0

References

Available upon request



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