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Engineering Electrical

Location:
Davis, California, United States
Salary:
100,000
Posted:
December 06, 2018

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Resume:

HERSHEL SHAH

**** ****** ***** *****, ** 956**-***-*** 1594 ac7v7x@r.postjobfree.com

SKILLS & ABILITIES

– C/C++

– Python

– MATLAB

– Verilog HDL

– *nix Operating Systems

– CUDA

– OpenCV

– GNU Radio

– BASH

EXPERIENCE

Electronic Systems Intern, Tesla June 2018 – September 2018 Palo Alto, California

– Analyzed factory data and made process recommendations to increase Radio Tuner FPY to 99%.

– Created BASH tools to reduce required number of engineers on field tests by 50% .

– Debugged and maintained radio firmware using C++ for all car models.

– Designed and implemented radio test suite decreasing testing time and automating test process.

– Created service to run remote commands on several engineering cars simultaneously. Wireless Engineering Intern, Tesla June 2017 – September 2017 Palo Alto, California

– Analyzed FM HD Radio Quality before official Model 3 release.

– Determined feasibility of In-Car wireless harness using Python and BASH.

– Analyzed link between antenna placement and QoS in cars using Python and BASH.

– Created RF test suite (Bluetooth, 802.11b/g/n, WCDMA, GSM, and LTE) using Python. Wireless Engineering Intern, Dolby Laboratories June 2016 – September 2016 San Francisco, California

– Determined wireless network parameters MIMO vs SISO, Antenna Polarizations, UDP vs TCP, MAC layer retransmission parameters for an advanced R&D project. RELEVANT PROJECTS

Sampling Rate Converter

– Implementing polyphase interpolation filter with several constraints to convert music between different formats using MATLAB.

Audio Denoiser and Classification

– Implementing a real-time audio denoiser and classifier on Raspberry Pi 3 using C. Parallelized Image Blending and Feature Extraction

– Implemented SIFT and RANSAC in CUDA and OpenCV to accelerate feature extraction.

– Developed firmware on Nvidia Jetson TX2 to blend consecutively taken images in real-time. 32/64-bit Primality Verification Machine

– Implemented 32/64-bit primality checker on an Altera DE-10 lite using Verilog HDL .

– Accelerated computation with 10 stage pipeline with parallelization resulting in 1 second runtime. EDUCATION

University of California, Davis – B.S. in Electrical Engineering

– Linear and Non-Linear Circuits

– Digital Systems I and II

– Computer Architecture

– Discrete/Continuous Signals

– Parallel Programming in CUDA

– Antenna Design and Analysis

– Probabilistic Analysis of Electrical and

Computer Systems

– Electromagnetics I and II

– Semi-Conductor Physics



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