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Design Engineer

Kingsville, Texas, United States
December 06, 2018

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**** * ********* *** *** #A Kingsville 78363 361-***-****


An Electrical Engineering Masters Graduate with over five years of experience in analysis, design, coding and implementation of innovative business solutions with good understanding of HDLC and SDLC methodology. Looking for a fulltime opportunity that utilize developed skills and education in electrical engineering, circuit design and simulations


Texas A & M University- Kingsville Texas

MS in Electrical Engineering –3.5GPA December. 2017

Bapatla Engineering College-Bapatla India

BTECH in Electronics and Communication Engineering –4.0GPA April. 2014


Verilog HDL, System Verilog, VHDL, MATLAB, FPGA, ASIC, CMOS, Xlink, Altera, Cadence DFX - Scan, JTAG, VISA, C, C++, Tcl, Perl, Python, and Java programming skills, Microsoft Office Package Team work, DFT, PLLS, DLLS, TX, RX, Soldering, communication skills, PCIe, NVMe, NAND, DDR and CPU sub-systems, customer relationship, persuasive.


VHDL, Verilog HDL, Principles of VLSI Circuit Design, Advanced IC Design, Digital Electronics, semiconductor fundamentals, Advanced semiconductor fundamentals, AC/DC Circuit design, Embedded system, Micro-Processor, Micro-Controllers, Digital Signal Processing, sampling and THESIS


Life Size Technologies Austin, Tx



Lead the efficient execution of test plans on multiple platforms, measure progress and metrics, and work with cross-functional teams to achieve these results

5+ years of technical “hands-on” leadership using multiple verification platforms: test bench, emulator, FPGA, software environments and system testing

Lead the development of test plans, building the necessary test bench infrastructure, developing tests and verifying the design

Proficient with industry standard tools and scripting languages for automation

Be a highly-valued member of our start-up like team through excellent collaboration and teamwork across disciplines

Texas A & M University January2017 – December 2017

Role: Research and Teaching assistance

Thesis: Near real time hardware architecture implementation for edge detection based on structured forecast edge method.

Description: The structured Forecast Edge method is used for finding a specific target over remote sensing images

This project code also helps us to track the locations of the ship that need to be identified which is the basic enterprise application such as in Military services and submarines.

Environment: MATLAB Version-R2012b, Xlink VHDL-93 V2001

Electronics Corporation of India Limited Hyderabad, India

DESIGN VERIFICATION ENGINEER November 2014– December 2015


Development of multi-faceted verification/validation strategies and plans that include advanced design verification, ASIC, emulation, software and full system testing

Successfully lead verification on multiple projects working with multiple levels of logic: IP blocks to SoCs to full system testing

Performs all aspects of the SoC design flow from high-level design to verification and system validation, to create a design database that is ready for manufacturing

Analyzed and resolved design related issues in a timely manner, reviewed and recommended improvements to existing designs.

Electronics Corporation of India Limited Hyderabad, India



Develop/Modify Perl/Bash/Python scripts. Develop System Verilog/UVM testbenches at Top/Sub-system/Block-levels

Develop the actual UVM DV Agent (Monitor, Driver, Scoreboard). Debug, report, and work closely with design engineers

Develop/Integrate C/C++/Matlab Reference models into the testbench. Communicate with the team and execute the test plans in timely matter

Bapatla Engineering college August 2013- March 2014

Role: Project Leader (Teaching and research assistant)

Project: Image enhancement and restoration for satellite Application Using MATLAB and Verilog HDL


Performed a requirement analysis for the Image with high quality. Design and development of the solution using MATLAB Framework, FPGA

Integration and functional testing. Analyzed work places for reducing work cycle time operations

Promoted implementation of Front end, Data model and Integration throughout each operation with current data

Environment: MATLAB Version-R2012b, Xlink VHDL-93 V2001, and Microsoft Office


FPGA Implementation of distance Measurement with Ultrasonic Sensor

Controlling of Device through Voice Recognition Using MATLAB and VHDL, FPGA

Simulation of a CDMA System Based on Optical Orthogonal Codes using MATLAB and VHDL

Image processing on FPGA using Verilog HDL and Matlab

Performance Analysis of InGaAs/InP Avalanche Photodiode by using different Guard Ring Structures Delay timer (LS7212) in Verilog HDL

Small projects like Automatic stair case Indicator, Automatic water lever indicator, Clap Switch, Etc.


Good Design knowledge, good basics of ASIC flow, Strong in Verilog/SV, VCS/Verdi etc. design Knowledge and/or experience in non-volatile memory design More knowledge on VCS/Modelsim, Synopsys Design Compiler, digital signal processing.

Excellent C, C++, Perl, Python skills Excellent analytical, problem solving and communication skills. Good System Verilog and OOP coding skills for verification Testbench development.

UVM knowledge is an asset, also known of VHDL/Verilog design and coding skills for synthesizable FPGA designs

Solid understanding of ASIC design flow logic design, verification, RTL coding, synthesis, timing and backend, also knowledge on Universal logic gates, basic building blocks, memory design.

Experience with Xilinx Zynq/Altera SoC ARM-based devices. Xlink VHDL V2001 used for Vivid covered Xilinx’s mid-scale and large FPGAs and ISE covered the mid-scale and smaller FPGAs and all CPLDs

Performs all aspects of the SoC design flow from high level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing

Proficient with Verilog and System Verilog HDL and design methodology, Design, implement, and debug complex logic designs on a block-level and full-chip level

Designing microprocessor based or embedded micro-controller-based systems, include HDMI, DisplayPort, MIPI DSI/CSI, I2S, TDM etc. Responsible to verify functional and power-saving features at IP & SoC level for multi-generation Platform Controller Hub (PCH) Chipset SoC targeting Server, IOTG, PC and mobile markets.

Developed test-plans, test cases in OVM/System Verilog, coded SV assertions & functional coverage to check design compliance with the architectural specs directing various blocks at SoC like PLLs, PHYs, Voltage Regulators, Clocking Unit to meet power targets.

Designed SERDES PHY components, PLLS, DLLS, TX, RX, etc. Digital and analog/IO circuit designer experienced with high speed digital, IO and analog circuits (e.g. PCI Express, HDMI, HT, USB, DP, SATA, etc.)

MATLAB programming. Understanding of MATLAP profiler and compiler, Knowledge of software engineering concepts, software design, and user interface design. MATLAB/Simulink, real time workshop, dSPACE/control desk. More knowledge on digital signal processing.

PSpice, used in integrated circuit and board-level design to check the integrity of circuit designs and to predict circuit behavior

Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs


Recognized as an expert in National Level Workshop on VLSI by PGP Electronics Private Limited.

Recognized as an expert in National Level Workshop on MATLAB Programming by BAPATLA ENGINEERING COLLEGE Bapatla.

Organized National Level Techno Management Cultural Fest in BABA INSTITUTE OF TECHNOLOGY AND SCIENCE vizag.

Certified as a professional VLSI, ASIC AND FPGA chipping Designer.

Recognized as an active member of ACC (Aggie Coding Club) by Texas A & M University-Kingsville.

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