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Engineer Design

Riverside, California, United States
November 28, 2018

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Woo-Young Yoon, PhD ***** Via Sherry

Riverside, CA 92503

949-***-**** (cell)


Applying for Read/Write Analog & Digital Engineer.


oMore than 25 years’ experiences of electrical engineering of research, design, validation, and Techniques & Methodologies from HDD, Tape drive, and Hybrid (Flash, SSD) drive.

oObtained SSD test training with Front-end Storage protocol like SAS, NVMe/PCIe from WDC test lab.

oSignal integrity (EMI, ESD, cross-talk, Audio Test and CMRR).

oDefine and validate PCBA, Flex Circuit, Preamp, and SoC, etc

oPower integrity (Power consumption and PSRR) by the PCBA and SoC optimization.

oThe analog signal and digital signal process for Preamplifier and SoC.

oPCBA related- validation, failure analysis, and solved the critical issues.

oDevelop the algorithm/feature to improve the test and process for the new technology.

oDevelop the test system for components to predict the end-product performance.

oVarious critical failures analysis to result in the great improvement.

oCapable of using Tableau, SQL, Python, JMP, C, LabVIEW, Linux, Spotfire, Minitab and Microsoft suite.

oVarious data analysis/management from the various DOE and factory’s larger data.

oWork closely with the program manager and the cross functional team, also suppliers (each components).

oProfessional - Confront problems, propose solutions and take ownership through to resolution. Have a positive can-do approach to work.


Western Digital Co, Irvine, CA (2012- Present)

Principal Engineer, Preamp/Channel Group

oKey contributor in design, validation, and techniques & methodologies of the HDD and Hybrid drive under SAS, SATA, USB application the various customer requirements.

oDefine and validate PCBA, Flex Circuit, Preamp, and SoC, etc.

oPrototype, Staging, and full product develop up to transferring to factory.

oDevelop and execute features/algorithms for the new technology that led to higher reliability and better performance product.

oPerform Analog signal integration for Preamplifier (front-end solutions) development.

oPerform digital signal process and validation for SoC in staging, optimizing, and full developing stage, and more following up the mass production.

oCollaborate with firmware debug FW engineer to validate and mature drive firmware

oOptimize the critical design parameters from SoC channel, Preamplifier, and Magnetic head/media, and sub-systems (PCBA, Flex Circuit, and testing).

oExecute EMI test (Audio, RF signal), compatibility, reliability by the critical design change or code, and components (PCBA, preamplifier).

oInvolved the in-depth channel and system characterization at 4 corner & various environments.

oInterpret and analyze customer specifications, and validation/execution.

oDevelop 2nd source for Preamplifier, SoC Channel, and sub-system (PCBA, Flex Circuit).

oValidate algorithm of test parameters/techniques for component audit at incoming.

oPerform the various DOE for the new materials, new designs, and test & process time reduction.

oPerform the various failure analysis from process & reliability and from the customer

oBig-data analysis (DOE and the factory Big-data) using various data analysis tools (Tableau, Spitfire, SQL).

Samsung Information System America (SISA), San Jose, CA (2006- 2011)

Senior Staff Engineer (Tech Leader), Recording Technology Group

oKey contributor in leading the universal preamplifier development for one bitmap, criteria, formula, and die size from the multiple suppliers.

Cost reduction and quality improvement from CMRR, PSRR, and EMI.

oDeveloped the sub-components (PCBA, Flex circuit) and testing systems for incoming.

oDeveloped and executed test plans and techniques and tools for components to have the best prediction to the drive level performance.

oResolved the Signal integrity issues (EMI/EMC/Signal Integrity/Power Optimization) by PCBA and optimization of preamplifier, obtained OEM qualification.

oPerformed the various failure analysis from process & reliability and from the customer.

Resolved ECC errors when the first 4K sector was implemented from 512 sectors.

For customer returns, and for process and reliability failures.

Utilized FMEA (Failure modes and effects analysis) for Preamp qualification.

oValidated FW code and closely working together for FW debug and FA.

oExecuted the great low cost for “No-Component Testing” and “Drive process test time reduction” and “developed the 2nd source of Preamplifier”.

oData analysis from every DOE and factory’s big data, and executed the corrective actions based on the data analysis à ~25% of the daily works.

oClosely working together with the Korea development center and factory for the on-going daily activities.

Western Digital Co, Fremont, CA (2005- 2006)

Sr. Principal System Engineer (Advanced Test Development Group)

oKey contributor in established and executed for the regular monitoring & testing system for every new wafer to check EMI & Crosstalk performance.

oLet EMI/Cross-talk task force team to solve/improve the high failure rate.

oDeveloped the innovative testing system to predict the drive level performance.

oValidated the new FW for testing for the new test board with the related code, Preamplifier and driver, and released test instruction and the related documentations.

oLed the failures analysis for EMI/Cross-talk related failures.

Quantum Corporation, Shrewsbury, MA. (2001-2005)

Principal Design Engineer IV / Lab Manager (Advanced Technology Lab)

oKey contributor in leading the advanced sensor design for DLT tape drive.

oValidated Magnetic recording sensors and sub-systems (PCBA and Flex Circuit).

oDeveloped the MTTF testing system to test the new sensors.

oDeveloped the component test system to predict the final product’s performance.

oPerformed the Failure Analysis from the process and customer return.

Seagate Technology, Bloomington, MN (1999-2001)

Lead Engineer (Magnetic Recording (Special) Sensor Development Group)

oKey contributor in qualified the world 1st wide writer and read sensor (Wafer process).

oDeveloped the sub-components and sub-systems to characterize to meet the various requirements due to the different customers’ design.

oDeveloped new test techniques and metrology to predict the customer’s final test result through the correlation with customers.


oPhD in the Engineering management, Warren National University, USA

oBSEE, In Ha University, In-Cheon city, Republic of Korea

My Skills and training

oTableau, SQL, LabVIEW, Linux, Spotfire, Minitab, MATLAB and Microsoft.

oLinux Server Management and Security cortication.

oSQL Essential training course from LinkedIn.

oCompleted Hybrid (HDD/SSD) drive integration course (Knowledge Tek).

oCompleted SMT (Statistical Modular Training) course.

oCompleted for SSD design / testing process training (on-site).

oCompleted PRML/NPML Channel for Data Storage training (Knowledge Tek)

oPreamp Design/Testing/Process at “Texas Instruments”.

oLean board (Similar to Agile) experienced – 3 times/week.

oCompleted Business Writing techniques and skills.

oGreen Belt course for Six Sigma.

oProject Management.


oUS Patent 6253445: Planar thin film head and method for forming a gap of a planar thin film magnetic head

oUS Patent 6091583: Planar silicon head with structure protected from over current / over voltage

o“Flexible Circuit Suspension Design “in processing for U.S.A patents. Issues on 1997

o“Head Design to prevent the head damage from the over current/voltage" Issued on 1997

oMagnetic Thin Film Inductive Head configuration to reduce the Eddy Current and the Undershoot problem" Got the patent from U.S.A / England / German. Issued on 1994


oLowering the cost of production of Hard Disk Drives by utilization of an innovative method of manufacturing and testing of magnetic recording heads (WNU ID 43876, Warren National University, June 21,2007)

oISBN: 0-7803-7647-1 Lifetime predictions due to electro migration failure in tape heads

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