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Engineering Computer

San Luis Obispo, California, United States
November 05, 2018

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916-***-**** • •


California Polytechnic State University, San Luis Obispo, CA September 2015 – June 2019 (Expected)

• B.S. Computer Engineering

• Cumulative GPA: 3.5

• College of Engineering Dean’s List: 6 quarters


Astranis Space Technologies San Francisco, CA

Engineering Intern – Payload Digital June 2018 – September 2018

• Designed and implemented additional functionality for an existing bench equipment automation test framework to provide a basis for future test scripts with background data logging and plotting.

• Utilized the test framework to create a test suite to characterize the ADC, DAC, and FPGA of the satellite’s SDR.

• Designed FPGA modules to conduct test pattern generation and error detection in order to measure the bit error rate of high-speed serial communication links. Trust Automation Inc. San Luis Obispo, CA

Engineering Intern February 2017 – September 2017

• Configured Jenkins CI system to work with existing build system to build and test current firmware projects.

• Designed system to detect which users caused certain builds to fail, these users were then notified by email.

• Wrote documentation explaining the system and gave a final project presentation to the firmware team.

• Completed various other engineering related tasks such as soldering, repairing existing circuitry, and adding functionality to an existing application that interfaced to a robotic arm test fixture. PROJECTS

Reprogrammable Guitar Pedal September 2018 – Present

• Currently designing an FPGA-based system to act as a reprogrammable guitar effect pedal as a personal project to solve the problem of needing to buy multiple pedals each with a single effect.

• Implemented the current system using the Digilent Nexys4 board with the Xilinx Artix-7 FPGA, the on-board ADC to sample the guitar output, and an MCP4921 DAC to drive out the processed signal.

• Project Link: LZW Compression May 2017

• Implemented the LZW compression algorithm in C using a trie to improve compression speed.

• Designed the program to work on both readable text files as well as binary files. RAT MCU March 2017

• Implemented the RAT MCU on a Xilinx Artix-7 FPGA on board the Digilent Basys3 development board.

• Designed and wrote a clone of the game Fall Down in RAT assembly to run on the processor.

• Project Link: Basyc Memory August 2016

• Designed and implemented a pattern-based memory game for the Digilent Basys3 development board.

• Implemented practical digital circuits such as signal debouncers and LFSR pseudorandom number generators.

• Project Demo:


Programming Languages: C, Python, Java

HDLs: SystemVerilog, Verilog, VHDL

Tools: Git, Make, GDB Debugger, Eclipse, Xilinx Vivado, Intel Quartus, LTSpice, Oscilloscope, DMM, Spectrum Analyzer RELEVANT COURSEWORK

Electrical Engineering: Semiconductor Devices, Digital Integrated Circuits, Analog Integrated Circuits, Continuous-Time Signals and Systems, Discrete-Time Signals and Systems, Classical Control Systems, Digital Systems Design Computer Engineering: Digital Design, Computer Design and Assembly Programming, Programmable Logic and Microprocessor-Based Systems, Introduction to Real-Time Operating Systems Computer Science: Systems Programming, Computer Architecture, Computer Organization, Discrete Structures

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