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Design Engineer Manager

Location:
San Jose, California, 95125, United States
Salary:
185,000
Posted:
October 30, 2018

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Resume:

Peter Roy Ateshian **** Pine Ave, San Jose, CA ***25

M: 415-***-****

H2: 831-***-****

ac7jpw@r.postjobfree.com

ac7jpw@r.postjobfree.com

ac7jpw@r.postjobfree.com

SUMMARY

Formed and built ‘Xt’rm’ DESIGNS LLC, a successful Technical Engineering Support, Business Development, Sales & Services Company that has been in operation for twenty years with as many as 50 people. Provided the leadership and technical direction for VLSI Full custom & ASIC design and complex EDA/CAD flows; including new RISC-V CHISEL Scala technology implementation applications for IC design. FPGA prototyping of RISC-V Yocto Linux, ARM7, ARM9 CortexM0/1 - CortexA8/9 based SoCs and multi-processor devices. TrustZone subsystems (TEE) ARMv7 32 & ARMv8a 64-bit. Hardware Root trust core. Secure boot TEE. Secured controlled access DRM and payment systems. BlockChains, Merkle trees, Smart Contracts, DLT distributed ledger technology, ring signatures, multi-privilege access keys, concealed addresses, hardware hashing algorithms and IoT device firmware implementation. Xilinx with Embedded Design Kit (EDK) Toolset: Xilinx Platform Studio (XPS). Systems-On-Chip (SoCs) Processors (PowerPC, MicroBlaze, Vivado, Zynq 7000-ARM) Virtex XC2-5. Intel's Altera Quartus II, Pro Prime Arria 10 HPS (embedded dual ARM Cortex A9) FPGA VHDL and Verilog Applications. Cyclone Virtex FPGAs cross porting Mentor Precision and Sagasi 3/4 and retargeting. FPGA ChipScope verification and debug. Recently work on NDA limited details for USB3, PCIe Gen3/Gen4, for Game systems, DDR3-DDR4-DDRx, Low Power DDRx, 4K+ HDMI, UHD, MIPI, Gigabit Ethernet. QSound psycho-acoustic 3D sound DSP and ASP algorithms in Silicon CMOS implementation. ICT QSound device. Android ADK Eclipse SDK Java apk dalvik Lua binary malware detection, DARPA-i2o APAC PI 2014/16. CAN hacking DARPA CAN bus and peripheral vulnerabilities project. Ida Pro x86 ARM reverse engineering. Kali RHE Ubuntu Debian Linux and BSD Unix kernel open source Raspbian drivers. Embedded Blind ROP ( brop) attacks, Pentest: penetration testing, open-vas, nessus, nmap, zenmap dirbuster, mxtool, the harvester, social Engineering, and Metasploitable2 Linux, CTF exercises. [Under NDA: NAML 2017,2018 Navy Applications for Machine Learning – Supervised Learning applied to MIMO optical communications; Telecom ESS5/6 AT&T Central Office Cisco & Avaya VOIP]. Experience (depth):

Digital logic and mixed signal analog design with RTL Verilog / VHDL / System Verilog Since 1987 SPARC FPGA ASIC ARM RISC-V TSMC IBM 45-22-14nm finFET and FDSOI design 20+ yrs

MATLAB – Describe in brief about your experience matlab: MatLab machine learning, symbolic mathematics, Communications simulation, SimuLink, HiL, since 2004 13yrs.

FPGA architecture and tools Experience in Brief: ebook on FPGA ARM Cortex and mixed signal Applications. Since 1992 Xilinx Altera Actel/MicroSemi Lattice started with Exemplar Logic acquired by Mentor Graphics Corp. Years of C/C++ code/programming experience Unix Linux C/C++since 1987 30+ yrs Forward Error Correction (such as Reed-Solomon, Turbo, LDPC, and Polar Codes) Satellite Communications FEC Reed Solomon, turbo has too much latency but good for space Communications. MIMO free Space optical (FSO) communication 2015 others since 2005, 13 yrs.

Digital Signal Processing such as filters, FFT, and wireless concepts Cyclotomic dsp filters, Intel 2910/20 since 1980 DSP pSoC FPGA 27yrs HLS, OpenCL, SystemC

Since 2010. 7 years

Algorithms.since 1987. 30 yrs interpolation, linearization, parallel algorithms mpi, Open MP, Intel TBB silc.

Linear Algebra, BLAS, such as matrix multiplies, ML & new AutoML applications, reduced precision high performance options.

Since College. On mCPUs since Matlab 2004 and spice3A6 /2g6. 1978. Movidius fathom Caffe TensorFlow.

Chronological:

1992 - 2004 Exemplar Logic FPGA EDA tool box for synthesis simulation of Verilog VHDL variants. XNF and CLB with LUT optimization. Mentor Graphics Corp, Conexant MindSpeed, AMD NVD. Finite state machine,FSM design, TMR space Applications TMR design. ASIC chip CPU Data path synthesis design and timing optimization. STA timing closure. Clock tree synthesis. Side channel Attack fault injection Attack crosstalk mitigation. Oracle SPARC Intel icg missiles x86 embedded dram. Military confidential DSP analog mixed signal Applications. 2007-2012 Actel Micro Semi fusion Mixed signal FPGA DSP ARM core Applications for US Navy. Development of eBook for NPS with limited distribution. 2012 -2014 Xilinx Vivado and Intel Altera neural networks Applications for radar pattern signature recognition. Sub pixel detection of dynamic target. OpenCV and open source libraries.

2014-2015 Femto Satellite swarm network Design internet of space (IoS). Intel IDF SF presentation 2016. Laser submarine optical detection system patent application. US Navy. ARM Cortex A 9 IoT c++ QR code demonstration. REST API Azure MQTT heroku Salesforce IBM Watson Bluemix node-red arm mbed-os RTOS 5.x Cloud connectivity REST API SOAP.

2015-18 US Navy underSea Lidar imaging and laser communications. NDA and Clearances preclude disclosure. FSO laser mimo communications with machine learning compensation. NDA and Clearances preclude disclosure. IoT Analog security patent application US Navy.

Raspberry Pi3 Debian Ubuntu Rasbian Python sciPy numPy QR code optical MIMO communications signaling Open CV C++ ARM IoT

ebook US Navy EC3800 course PSoC-ARM Design

‘Xtr'm' Designs LLC, was initially funded by Mentor Graphics, TeraSystems, Conexant, US Navy and SUN Microsystems. 2018 - 2009 Clearance level: TS/SCI Business Development: Six consecutive years in Achievement Club for over Quota Performance $2M+ and Technical excellence. Five startups with IPO and M & A exits.

Recently:

IoT REST API MEMS sensors C++ and ARM assembly drivers, developed mbed device connect ARM network and SensorTile, ST Microelectronics, IBM Watson bluemix node red, heroku Salesforce, zebra's zatar network, postman Cloud connectivity. QR code barcode reader video camera app text conversion then WiFi or wired transmission to cloud for analytics. IoT details: C++ www.mbed.org see GR Peach video QR code reader using ARM Cortex A-9 Series, rtos mbed-os listed under Xtrm Designs LLC; Python and Raspberry Pi 3 quad ARM Cortex A-53 Series/Raspbian OS NPS CS Department course CS2020. C++ SensorTile ST Microelectronics two Processor Cortex M0 and m4; Intel Arduino 101 C++ D2000 Curie SoC with Arc, ARM Cortex M0 and Atom/x86 tri Processor and integrated MEMS sensors. TRNG and next generation Iridium modem Femto Satellite. IDF SF presentation, award winner hands-on lab. JTAG IEEE 1149.1 BFM (bus functional models) SoC ASIC FPGA Verification IP for UVM Methodology with Verilog/VHDL variants.

TCP/IP - Fusion TCP/IP v4 & v6 Dual Stack, IPv6 Phase-2, ANSI C, ARM Cortex A-Series, Cortex M0 series, Intel Curie SoC ARM devices from different vendors and Nordic Semiconductor nRF51DK and BLE beacon Cortex M-series. Python 3.7 Applications Raspberry Pi 3 using Linux Raspbian, Intel Joule 570 platform Linux Ubuntu See GR-PEACH on www.mbed.org Prior work Telecom and ESS5 AT&T Central Office CISCO & Avaya VOIP (under NDA). RF: WiFi 802.11ax 60GHz and WiMAX 802.15, Satellite communication, CDMA OFDM Spread Spectrum RF, Femto Satellite swarm Design, wireless HDTV 60GHz, Optical: US Navy work - Tera Hertz laser FSO free space optics OOK modulation communications and Submarine (underSea) optical Laser communications. See my 2015 IEEE security and privacy, MAPLD-SEE, CHES Cryptography UCSB, ARM TechCon, IDF SF Intel developer forum 2016 EDPS RISC-V EDA Chisel/Scala unfair advantage talks. Undersea LidaR imaging and laser communications, patents in process, NRP funding; analog security TRNG patents in process.

Femto satellite swarm design, protected TRNG based satellite communication RF and laser with modulating retroreflector (MRR). Work with Breakthrough Starshot organization UCSB NASA.

Technical Marketing: Talks and presentations at Sensors, MAPLD-SEE, IEEE security and privacy, DARPA-VET- FPGA hardware Trojan detection by power spectral analysis; RISC-V Chisel EDA Benefits EDPS Monterey, CHES Cryptography UCSB, ARM TechCon, Intel developer forum (IDF), Embedded Systems Conference (ESC) in 2016 & DARPA-SHARE, API World hackathon and presentation 2017.

Tactical missile design, two stage, flight safety system (FSS), booster and sustainer transonic to supersonic design. China Lake, Point Mugu testing. RTOS and ROS SLAM trade-offs. Harmonic Rate Monotonic algorithms (Barr) and Custom memory management to mitigate memory leaks.

MAJOR CLIENTS INCLUDE:

ONR, NRL, JIDO DTRA, Riscure North America, Renesas Electronics America, Conexant Systems, Jazz Semiconductor, MindSpeed Technologies, USA Navy/NPS, Mentor Graphics, SocialEars, E TeraSystems, Arithmetica (APD), AMD Memories, CPLD N.V. Division, Intel ICG, Sun Microsystems, Rockwell Semiconductor, Alpha Industries, Sp3, KLN, ThermaWave, ARM Inc., Ikanos Communications, LSI LOGIC, Exemplar Logic, Parsec Software.

MANAGED SPECIALIST MULTI-CORPORATE MULTI-NATIONAL TEAMS OF UP TO 25 PERSONS, 3 CONTINENTS, FOR HIGH INTENSITY EXTREME VISIBILITY PROJECTS.

These included:

Multiple IP (ARM7, ARM9/ 11 Cortex, SPARC, DSP, Analog mixed signal IP cores) integration, benchmarking and SoC designs

NPS Femto Satellite redesign

Undersea LiDaR research and development

Synthesis and Scan design regression, TRW, SUN, Mentor Graphics, C, C++, OOP

200-400M Device Tape-out and silicon failure analysis (FIB) for major worldwide and domestic corporations. Mentor Graphics, AMD Memories, NVD CPLD Div., Intel ICG, Sun Microsystems, Conexant Systems, MindSpeed Technologies, Jazz Semiconductor, ARM, Ikanos Communications, LSI LOGIC.

Over 50 major projects at critical Time to Profitability. RET and OPC technology deployment at INTC, AMD since 1999.

Research in multi-hop ad hoc wireless radio and sensor networks (CISCO SYSTEMS Govt. Div. Rajant Networks).

Experience with real-time satellite ad hoc real –time bandwidth assignment

(COMTECH TEL).

CMOS RSNS A/D converter design for low power micro morphing air-land UAV and Autonomous Robotic Systems.

Emergent distributed Markov chain based multi-agent operating systems.

Detailed experience with real-time embedded, C, C++, UNIX, Linux, Minix and modified Windows operating systems.

Silicon-polycrystalline Diamond new device technology advances (Sp3) for GaN & InP HEMTs.

Taught courses and completed research in ARM9 embedded control systems, SoC integration C, C++, Linux, Minix

CMOS RSNS A/D complete device design in three CMOS processes (0.35u, 0.25u, 0.18u simultaneously,

Modern operating systems, TinyOS, Minix, IOS, SoC Real Time applications

Satellite /Spacecraft communications engineering, DSP technology (BDTI).

Developed specialists for independent contracting in Integrated Circuit HLVS, OPC-HDRC, and RET.

Synthesis analysis, formal verification, debug and redesign.

IBM Agile software Development and JAVA eclipse

ADT Android malware Java forensics DARPA APAC

Software Systems Engineering RTOS/ARM for scaled autonomous systems. Agile / Scrum workflow.

C#, Microsoft. .NET project testing, verification and validation.

MatLab M, DSP, OFDM, AM, FM, QPSK, symbolic mathematics, analytic optimization, control system transfer functions, VHDL conversion to FPGA, rocket dynamic wind shear stability, analytic hierarchy process (AHP). RECENT TECHNICAL SUCCESSES AND AREAS OF TECHNICAL COMPETENCY:

Mixed Signal SoC and ULSI DFM production Tape-out using Hierarchical HLVS and HDRC

Managed the updating of Analog, Communications, MATLAB 2006 - 2016b and Digital Labs courses to use Switched Capacitor Filters, CrossBow/Xbow, AM, FM, QPSK, OFDM 802.11, VLIW DSP, ARM9 technologies.

Debug techniques to isolate synthesis, library, and Place and Route design/tool/CAD flow faults - Completed for 15 Silicon Valley Clients

Developed e-books on Sakai and BlackBoard for 12 courses in the fields of DSP, Analog Communications, Digital Logic and Embedded ARM based SoCs

& FPGA PSoCs

Digital and Satellite Communications, A/D, OFDM, FFT, IFFT, FEC, Adaptive Superframes, PSK, QPSK, QAM

Winning ASIC Synthesis benchmarks with Exemplar Logic

(Precision/Leonardo) at SGI, Apple Computer (also FPGA), Sony, Ampex, Hitachi Microsystems, NET, Fujitsu, Lattice and Xilinx.

Switched Capacitor Circuits and Filters, Matched Z transform, Clock/Power Noise Alias reduction techniques

Switched Capacitor Filter Array Reticon R5626

Silicon Microphones (Surface MEMS), MEMS(Bulk) Relay and magnetic circuits

Psycho-Acoustics (Phase distortion/obliteration, 3D, QSound)

Digital Circuits Techniques, Polynomial Counters, Fast Pascal triangle adder and encryption circuits, Verilog, VHDL

Analog RF circuits on-chip LC circuits, Mixed Signal SOC integration, HSPICE

ELDO (Analog Mixed Signal solutions from Mentor Graphics Corporation) Microprocessor circuit timing and area performance optimization, PEARL, Mach TA, CPF, DC, PrimeTime, Critical path Spice net extraction Digital Cyclotomic Filter one bit A/D, Custom DSP AMD Bit slice, Intel 2920/10 A/D+DSP device for DTMF signaling, TMS320-MVP, VLIW use in DSP applications, ARM 7-9 Micro Controller Hard silicon-cores IP synthesis validation, benchmarking and Verification for SoC applications, Low Power CMOS Circuit synthesis techniques for medical devices, CSEM Zero Power Libraries for watch and minimum power application - Zero Power input transition Detection circuits,

PROFESSIONAL EXPERIENCE

Xtrm DESIGNS LLC

7/1992 - Present:

CTO / Founder /Principal

Engineering & Technical Consulting/Services Company supporting IC design, implementations and use of tape-out verification EDA tools for clients. Naval Postgraduate School, Monterey, CA 2004 - Present Adjunct Professor under US Navy contract to the Naval Postgraduate School, then employee 2006, responsible for CAPSTONE courses which are reviewed by ABET. 3/2004 – 09/25/2006 CCR Contractor then 09/26/2006 – present Federal Employee.

Researcher in Diamond substrates for thermal management in High Energy Electronics

Applications InP, GaN HEMTs.

Wrote E-book for EC3800 “ARM Synthesizable SoC Design with Electrically Erasable FPGAs with Mixed Signal Applications”

Production Design Tape-Out Flow: Completed Four Intel ICG (Missiles) Mixed Signal (0.13u-0.25u) Integrated Circuit Tape-outs with Calibre HLVS-HDRC Mentor Graphics EDA tool suite/CAPI-viafill and Star RC-Apollo Synopsys/Avant! Place and Route/RC Extraction tool flows. All four devices are Production quality on First pass silicon. This was used as a repeatable Success benchmark for internal INTEL M&T/ICG references. Completed LVDS 0.18u design libraries for ICG/Intel M&T analog group. Worked very briefly with Intel Litho Group on PSM corrections on gates - Training and benchmarking OPC/RET test-cases. Assisted in deep deployment on Calibre into IMS/IME and ICG M&T as Synopsys Hercules continued to fail on Key design.

Completed AMD Integrated Circuits assessment of <100-75nm technology shrinks on K9 microprocessor devices with Calibre Litho/PSM.

Completed AMD Flash NVD Device 369 Calibre HLVS/HDRC Tape out resulting in AMD-MGC/MCD First Pass Production silicon Success Story. Reduced runtimes from 15 hrs to 17 minutes by curing critical flow/Net list issues and using Multiprocessor (turbo) modes.

Completed AMD Y2K corrections of Calibre/IC rules for entire NVD rules suite for CS19 to CS59 due to OPPOSITE command EDA software code change. Flare angled ESD devices and diagonal gate devices are now all correctly checked rather than being deleted.

Completed Ikanos Communications 0.18u Mixed Signal Aztec Tape out with Calibre. Ikanos is now reviewing Calibre xRC their outsource P&R contractor uses Simplex (Fire, Ice, Thunder & Lightening).

Completed SUN Microsystems Gemini block conversions using Calibre HLVS and Simplex flows for RC extraction. Identified flow issues with feedthroughs and lost nets/Ports.

SUN Microsystems-

o Developed Lsim circuit simulation verification for FP Multiplier Mega-cells with Dynamic FF with static keepers and stacked gate logic for clock/power disable and full scan.

o Diagnosed circuit failures in decoupled clock header circuits with power and scan control due to clock skew on project Cheetah.

SUN Microsystems –

o Delivered Production solution to extricate flat GDS2 layers from Silicon Ensemble and rebuild with CheckMate when Cheetah database was too large to allow hierarchical output. o Calibre was used to independently verify database reconstruction. Runtimes for Calibre was in Hours while Dracula/Diva was in Days.

Conexant/MindSpeed/Rockwell Semiconductor-

o Assisted CAD/Design Groups in deployment of Calibre to replace CheckMate/Hercules/Dracula in 13 processes ranging from EEPLD/Flash to RF-Bipolar. This was completed in a period of 11 months - only legacy devices were run on Dracula/CheckMate. o Converted Bipolar RF design to newer BiCMOS technology and verified design with Calibre. IP reuse required Converted ARM9 Core to be verified, benchmarked and cataloged for next generation process.

o Installed and deployed Calibre as Key Verification tool in Conexant IP re-use programs using ARM7, ARM9 core and benchmarking as three way example.

Other activities include:

o Calibre successes at Silicon Access Networks, LSI Logic and Siliconix. o WiLAN OFDM G3 device Design and Specification for fading channel voice point to point communications prior G2 design was based on TMS 320 core DSP. Redesigned an OFDM VLIW and ARM based solution with WiLAN team.

o Mapped an Obsolete TRW Avionics ASIC IP from Motorola device into current ATMEL technology.

o Design and EDA Clients included TRW Avionics, AMD-NVD, Sony, Fujitsu, ARM, TeraSystems and Silicon Perspectives/Cadence.

ICT Inc. July 1994 - March 1996

Vice President Engineering (Contracting)

o Product redeployment of 22 of 27 EEPLD products with corrected design and production flaws over an 18 month period. o Introduction of a Zero Power Complex EEPLD to compete in the 5-7ns arena.

o Tools were Virtuoso/Composer/Dracula and Mentor CAECO. Cool RISC uP from CSEM Switzerland as a new Zero power technology for ICT.

o EM Marin SA Switzerland was approached to purchase ICT o ICT Lost funding as a restart in 1996

.

Parsec Software Dec 1993 - July 1994

Vice President Sales (contracting)

o Pearl - Mixed Mode/Hierarchical STATIC Timing Analyzer o During the 8 month period I completed sales with Texas Instruments, Fujitsu, Hitachi, Mentor (design group), AT&T, and IDT/QED.

o Company was sold to Cadence.

Multi-Source Integration 7/1992 to 7/1994

President (Sole Proprietorship of Technical Engineering Support/Business Development/Sales Consulting & Services Company which morphed into Xtrm Designs LLC

Consulted on SUN uP Tsupernami/Spitfire/Cheetah/Gemini and Three AMD Flash devices, QSound analog SCF 3D Sound devices and Hearing Aid/Cell Phone MEMS microphones.

Submitted SBIR for MEMS Microphone Study using Draper Labs device.

TRW-Consulted in the redesign of several Obsolete Military Devices into current technology

Exemplar Logic 5/1991 to 7/1992

Applications Engineering of Synthesis Applications Support / Sales to: Apple, Silicon Graphics, CISCO/StrataCom, Hitachi, Ampex, LSI Logic and EPSON. The company was acquired by Mentor Graphics. Mentor Graphics/Silicon Design Labs /Silicon Computer Systems March 1985 - May 1991

Technical Engineering Support/Business Development/Sales Consulting & Services Company

Strategic Technical Account Manager:- SUN & APPLE -completed $2.8M in first year. Over Quota six years in a row

Technical Account Manager - Silicon Valley territory $2.0M Engineer/Apps Manager: - Over Quota six years in a row. Design Manager San Jose for SDL - Apple Graphics Display chip PRIOR COMPANIES:

Atari Home Computer VLSI Design Engineer 1983-1985 Cost reduction and power conservation with CMOS conversions for DRAM Controllers and PLD devices. Eliminated LC timing delay lines that were unreliable in production due to humidity construction factors. Implemented polynomial counter circuits for video and timing functions for AT520 next generation computer. Design robotic circuits and controllers for independent operations and master controller.

EG&G Reticon Analog Design Engineer 1981-1983

Switched Capacitor Filters for 2400 - 19.2Kbd analog modems, SCF programmable array device, EDA tool development for the conversion of continuous time pole/zeros to Matched Z transform Filter poles/zeroes into Capacitor shapes/Arrays in GDSI and GDSII polygons.

Plantronics Design Engineer 1979-1981

DSP for Cyclotomic Digital Filters using one bit A/D and 2900 Bit-slice AMD uP and Switched Capacitor Filter implementation of 30 channel multiplexed DTMF filters.

EDUCATION:

(PhD) student Naval Postgraduate School computer science and systems engineering 2019

Master of ENGINEERING 1979 UC Berkeley (3 year program) - Combination EECS and Business Admin Dual degree Equivalent to MBA + MSc Bachelor of Science 1976 UC Berkeley - Engineering Science- Medical Engineering SLAC Summer Science Student - Nuclear Physics - Computational Physics Stanford Linear Accelerator Center SLAC 1974/75

University of London Passed 10 “O” Levels in one sitting 1972 (Math, Applied Math,

Physics, Chemistry, Biology, Art, Geography, French, History and English Literature)

PUBLICATIONS:

2018 NAML – Supervised Learning for Mimo optical communications. 2017 DARPA SHARE Project – Femto Satellite Swarm Design Femto Satellite Design TRNG Internet of Space presentations at Crypto/CHES 2016, ESC 2016, ARM TechCon 2016, Intel Developer Forum (IDF) 2016 Automated FPGA Trojan detection testing 2016 ITEA CYBER Workshop Automated Testing for hardware Trojan detection 2015 IEEE SECURITY and Privacy conference

MAPLD/SEE TRNG from SEU in RAM for Space protected communications FPGA hardware Trojan detection by differential power spectral analysis 2015 MAPLD-SEE conference

Programmable Filter Array Product - CICC 1983

AMD Non Volatile Production First Success Story 2001 (Mentor Graphics Consulting Publication)

ICT EEPLD Application Notes for Zero Power devices ASCF - Automated Pole/Zero Z transform to Capacitor Sizes/Shapes (EG&G Reticon proprietary Software)

Application Notes for IC Design and Debug (AMD Proprietary) DSP/SCF/Bit-slice Tradeoffs for DTMF/PSK signaling (Plantronics Proprietary) US Citizen, languages French, Spanish from high school REFERENCES:

Walden C Rhines CEO Mentor Graphics Corp

Rick Brown VP Micron

Gary Schottmer, VP Sp3 Inc (sp3inc.com) Mtn View

Surendra Rathur, Intel ICG San Jose

Chris Ward ARM Austin TX

Sunil Nanda ThinKit CEO/Level1 VP/Intel ICG GM

Papken DerTorossian Chairman of the Board ThermaWave Ward Vercruysse, Intel/Oracle /SUN Microsystems

Anup Mehta, Intel/Oracle /SUN Microsystems

Uday Kapoor, Fujitsu/SUN Microsystems SPARC IP core/tools Chin-Fu Chen, Qualcomm (ARM cores)

Ravi Ranjan, Conexant (ARM7 ARM9 cores)

Andy Brotman, Global Foundries/MindSpeed

Mark Santoro, Oracle /SUN Labs, Juniper Networks/Micro Magic CEO



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