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Engineer Process

Location:
Granada Hills, CA
Posted:
October 25, 2018

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Resume:

AVAG AVAGYAN

***** **** **., ******* *****, CA **344

Tel: 818-***-****, Cell: 323-***-****

E-mail: ac7h0m@r.postjobfree.com

OBJECTIVE: To obtain a challenging position as an Engineer in Research, Development

and Manufacturing of Semiconductor Devices and integrated-MEMS ICs.

SUMMARY OF EXPERIENCE:

Strong Background in the following areas:

Physics of semiconductors and semiconductor devices;

In depth knowledge of theory, processing and application of semiconductor devices;

MEMS(Micro-Electro mechanical Systems) design and processing;

Theory and Technology of Bipolar and CMOS devices and ICs;

Hands- on experience in the following process areas;

Oxidation and diffusion, Ion Implantation, Photolithography and Wet Etching.

Thin Film Deposition, PECVD, LPCVD, MOCVD, Sputtering, (RIE) Dry Etching.

Wafer planarization methods such as CMP, grinding, lapping, and polishing.

Electroplating of metallic components.

CMOS Front-end and Back-end Processing.

Wafer to wafer bonding.

Packaging of semiconductor devices and integrated MEMS elements.

Sol-Gel processing for microelectronic chemical sensors.

Bulk Micro-machining, Surface Micro-machining (Silicon KOH and TMAH etching).

Failure analysis and reliability of MEMS devices and ICs (SEM, FIB, etc).

Microelectronic hybrid processing (Wafer & Die Processing, SMT,Die attach, wire bonding)

Hands on experience with process development (to reduce process variations) and product yield improvement. Proficient with DOE, SPC, DFMEA and PFMEA efforts during process development and production. Strong problem solving, project management and teamwork skills.

Hands on experience with Tanner EDA layout (L-Edit), DRC and Coventor simulation tools. Experience with AutoCAD and SolidWorks.

Project Management and Supervision of a group of Engineers and Technicians in Manufacturing.

Taught undergraduate courses in:

Properties of semiconductor materials, Processing of semiconductor devices and ICs.

Analysis of crystallographic structure of solid state materials by X-rays, SEM.

EMPLOYMENT HISTORY:

Apr. 2015- Present H2 Energy Renaissance, Los Angeles, CA Sr. R&D Scientist.

New process development. Process optimization and control. Quality control.

Nov. 2012- Present Semiconductor and Solar Sells Processing and Design Consultant

Technical Consulting Services, including:

Research management. Operational management. Project management. Quality control.

R&D Consulting: New process development. Process optimization. Process control. Product development.

July 2011- Oct.2012 International Rectifier, Inc., El Segundo, CA Sr. Process Engineer

Responsible for Diffusion, High Temperature Drive, Thin Film (LPCVD and PECVD) and Wet Chemical Cleaning processes and tools in a Silicon wafer FAB. Tools included APEX System controlled BTI horizontal furnaces, Novellus Concept1, and FSI-Mercury systems.

Responsible for process development, sustaining, optimization, control in diffusion area to achieve high yield and reduce cost and cycle time in Silicon wafer FAB.

Sept. 2008- Oct.2010 International Solar Electric Technology, Inc. (ISET, Inc), Chatsworth, CA

Sr. Process Engineer

Developed and optimized MOCVD ZnO (doped with B and Al) deposition process.

Developed and optimized CBD Cadmium Sulfide (CdS) deposition process.

Managed group of engineers and technicians for CIGS solar modules design and processing.

Nov.2000-June2008 Kavlico Corp., Moorpark, CA MEMS Process Development Engineer.

Designed a new process for MEMS Pressure sensors based on ASIC on SOI technology.

Teamed with other engineers in the design of new integrated MEMS capacitive pressure sensors.

Developed a new sol-gel process for microelectronic humidity and gas sensors.

Optimized Silicon-SOI wafer fusion bonding process.

Designed small size pressure sensors for medical application.

Developed a low temperature 6” silicon wafer bonding for MEMS application.

Improved Cpk for wafer bonding process from 1.1 to 1.7.

Reduced silicon diaphragm formation cycle (15%) by process consolidation and better manufacturing planning.

Determined a few root causes of the major failure modes in capacitive MEMS based Pressure sensors, which improved manufacturing yield by 14%.

Developed a new process for MAP pressure sensors using DRIE via etch of silicon wafers.

Conducted reliability tests for new designed MEMS pressure sensors.

Developed design and process specifications.

Managed group of technicians and operators.

Mar. 2000-Nov.2000 Global Communication Semiconductors Inc., Torrance, CA. Engineering Technician.

Teamed with engineers in the development of low stress silicon nitride PECVD process.

Working with engineering to develop new process steps and utilize steps on new equipments for manufacturing A3B5 devices (InGaP and InP HBT and GaAs PHEMT).

EDUCATION:

MSEE Moscow Institute of Electronic Technology, Moscow, Russia

BSEE State Engineering University, Armenia

PUBLICATIONS AND PRESENTATIONS:

Sixteen journal papers and presentations.

Three patents.

REFERENCES: Available upon request.



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