M. David Webster

** ********** *****

Poughkeepsie, NY 12603

Mobile 845-***-****

ac7fwo@r.postjobfree.com

SUMMARY OF QUALIFICATIONS

Experienced Six Sigma semiconductor engineer with creative and effective leadership skills. A history of leading high visibility, high value projects and delivering innovative, on time results. Extensive experience in designing and implementing enterprise wide solutions with an international scope. CERTIFICATIONS and AWARDS

Certified LEAN Six Sigma Greenbelt

Certified Project Management

Design of Experiments

Vice Presidents Accomplishment Award

PROFESSIONAL EXPERIENCE

IBM / GLOBALFOUNDRIES Senior Member of Technical Staff Lithography Development Engineer, Advanced Silicon Packaging

● Project Manager and Technical Coordinator for Canon Lithography – Led a team from the initial project definition to the on-time installation and qualification of leading edge lithography platform. $10M Project

● Developed Silicon Photonics laser attach integration process.

● Led a team that installed and qualified Flux Apply manufacturing tool. $1M Project

● Qualified Flux Clean manufacturing tool.

● Specified advanced NC-Flux materials.

● Provided Lithography solutions for Silicon and Glass Interposers.

● Developed Lithography solutions for multilayer RDL wiring.

● Trained Engineers in Minitab and Design of Experiments.

● Project manager for Joint Development Agreement project with TEL-NEXX resulting is a First of a Kind Immersion Agitation photoresist strip platform for advanced chemical processing. $4M Project

● Technical Coordinator for JSR photoresist

● Technical Coordinator for TOK photoresist

Process Improvement

● Led a team that resulted in 30% improvement in Linewidth Uniformity for 3D Technology for electroplated Gold plating process

● Led a team with DMAIC process and DoE to solution optimum lithography process conditions for Lead-Free Plating baths

● Led a lithography process improvement team that developed and implemented a 5% yield improvement at wafer test

NXP Semiconductors

Senior Process Development Engineer

Selected to plan, manage and provide leadership for 16,000 unit Reticle program that directly impacts the quality of $230 million annual sales of semiconductors. Provide interface with suppliers to improve all performance metrics. Lead Quality Assurance of all Deep UV and sub-micron Reticles. Develop asset control system to improve availability and reduce cycle time. Develop Reticle Qualification protocol to reduce business risk. Provide leadership with responsibility of launching site wide Lean Six Sigma Program. Accomplishments

● Lean Six Sigma Projects. Successfully lead two DMAIC projects. 56% Reduction in PS Linewidth Variation. Led a multifunctional team that characterized and improved the photolithography process which resulted in a 17% improvement at customer test. Process variation was identified and reduced in the post apply bake, post exposure bake, and developer modules.

Reticle Dependant Yield Improvement. Multimillion dollar savings and cycle time improvements were realized through statistically designed reticle improvements. Managed a multifunctional team that identified reticle defects, qualified a design change, and converted all production to new design resulting in 8% higher yield at the customer.

● Lean Manufacturing Led an international team that included IT, Engineering, suppliers, and operations that reduced reticle service time by 80% by linking shop floor to service supplier.

● DMAIC Worked with Senior Management to define the scope of Greenbelt Projects to effectively implement DMAIC

● DMAIC Review Board Advised Lean Six Sigma Greenbelts at weekly review of ongoing projects.

● Training Engineers Established an in-house training program and trained 50% of engineering staff on Process Control Plan system.

● Greenbelt Coach – Coached the Metrology Engineer through a Green Belt project.

● Process Development Qualified a replacement resist for FEOL layers

● Lean Six Sigma Greenbelt Conducted Gauge R&R studies on Linewidth and Resist Thickness measurement tools to ensure Repeatability and Reproducibility of measurement tools

● TS 16949 Wrote TS-16949 Procedures and developed training modules for; SOP, Training Plan, OCAP

● Supplier Qualifications Negotiated tighter specifications with Resist Suppliers. Qualified a new reticle supplier. Qualified a vented pellicle system that allows for less reworks and defects and also lowered the risk for customer yield loss.

DuPont Photomask/Schott Lithotec

Engineering Group Leader

● Project Management. Team Leader of 16 indirect reports for the installation and start up of $20 million cleanroom manufacturing facility. Led daily operations of Engineering Team; Cleaning, Metal Deposition, Photolithography, and Inspection.

● Team Leadership Led Product Qualification Team of 12 indirect reports for advanced Mask Blanks Qualification. The team included Engineering, QA, Manufacturing, Facilities, and Maintenance. The scope of the project was; pilot production, conformance to specification, leading weekly product performance meetings with customers, writing/auditing Standard Operating Procedures, auditing

“Design of Experiment” settings prior to run, interpreting DOE results, and transferring advanced process from Germany to US operations

● Team Leadership Lead/Coordinate Production-Engineering-QA groups for the manufacturing of 45nm advanced Blanks

EDUCATION and TRAINING

EDUCATION BS Physics, SUNY Plattsburgh

TRAINING

Lean Manufacturing

Six Sigma DMAIC

Value Stream Mapping

Design of Experiments

Process Control Plans

Project Management Training

Global 8D, TS-16949

FMEA

Statistical Process Control

ISO-9000 Standards

Common Sense Problem Solving

Leading Effective Teams

Microlithography – RIT

COMPUTER SKILLS

Minitab,Visual Basic, Microsoft Office – Access/Excel/Outlook/Project/Word/Power Point, Google Suite PUBLICATIONS Mobile Metrology for Advanced Photomask Manufacturing SPIE 11/2005 High-Speed Removal of Thick Negative Photoresist in Advanced Packaging Applications IWLPC 10/2014

PATENTS US Patent # 6758669 Variable Surface Hot Plate for Improved Bake Uniformity of Substrates US Patent # 6576572 Method of Heating a Substrate using a Variable Surface Hot Plate for Improved Bake Uniformity of Substrates

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