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Engineer Design

Bridgeport, CT
October 16, 2018

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Masters graduate with * +years of hands on experience in embedded control systems.

Excellent analytical and trouble shooting ability with good interpersonal skills, willingness to learn and grow with the new process and technology.

Hands on experience with CAN tools – Vector CANalyzer.

Good working knowledge in protocols like CAN, LIN, FlexRay, TCP/IP.

In depth knowledge of python scripting language.

Proficient in MATLAB/Simulink System Model Development, State flow and Target Link.

Familiar with MS-Office, CANdb and Visual Studio, lab equipment such as functional generator, oscilloscope.

Got hands on experience on using SVN Tortoise (Repository Tool), IBM Rational Doors (Requirement Management Tool).

Experience in Defect Management Tool JIIRA for logging and Tracking the Issue.

Played key role in ensuring the timely deliverables of hardware, software & calibration inputs associated with the HIL(Hardware-In-Loop) testing using DSpace and ETAS.

Expertise in using Trace Window and DTC Monitor in CANalyzer to check the CAN Communication and Diagnostic Trouble Codes.

Experienced on Working Different modules like BCM (Body Control Module), TCM (Transmission Control Module) EGC (Electronic Gauge Cluster), ECM (Engine Control Module) and PCM (Powertrain Control Module).

Microprocessor Concepts: Watchdog Timers, Interrupts, Timers, UART, SPI, I2C, GPIO and Memory Types (RAM, ROM, EEPROM etc)

Model-Based Programming: MATLAB, Simulink, MIL, SIL AND HIL simulations, Rapid prototyping and Automatic code generation using Target Link

Requirements and Configuration Management tools: Synergy and DOORS

Software Development Cycle: Agile software development, CMMI environment, CAN, LIN, Serial and parallel communication and CANalyzer

Software Testing and Tools: Static analysis, Unit Testing, Integration Testing, Regression Testing, Blackbox vs White box testing, D-Space based Testing functional safety concepts (ISO 26262), ASIL levels, and Diagnostic Trouble Codes (DTC).

Operating Systems: RTOS and Embedded Linux

Scripting Language: python



Vector CANalyzer 10.0, IBM DOORS, Dspace Hardware in loop (HIL), LT-Spice, Dimond Logic Builder.

MATLAB, Simulink, PSpice, LabView.


Embedded C, MATLAB Scripting, C & C++, python,8085 assembly language, Verilog (RTL).

Communication protocols

TCP/IP, CAN, LIN, J1939, Ethernet, Bluetooth, WIFI.

Operating Systems

Windows XP/7/8, Linux, MAC


Woodward ECUs, Kvaser CAN, Vector CAN Interface VN1630, Nexiq USB-Link 2.

Transmission: Allison, E

aton & ZF (8Speed, 9Speed)

Brakes: Hydraulic Brakes & Air Brakes

Engine: Cummins Diesel Engine, Navistar Engine & Gasoline Engine.

Embedded Peripherals

UART (RS 232, RS 485), I2C, SPI, CAN.

Test Equipment

Oscilloscope, Spectrum Analyzer, Function and signal Generator.


Client: GKN Automotive June 2017 – To Present

Role: Validation Engineer

Responsible for system level testing of powertrain controllers including Transmission and drivetrain modules.

Responsible for conducting Design Failure Mode Effects Analysis (DFMEA) for control logic changes.

Work closely with platforms, core teams and module suppliers in developing features and associated test procedures for those features at the powertrain system level.

Responsible for the integration and validation of Transmission and Driveline software and calibration on a HIL/vehicle testing environment.

Develop and manage controller integration deliverables such as system schematics, Design Verification Plan & Requirement (DVP&R) for multiple vehicle lines.

Report component and system level issues using CAN tools and calibrate powertrain performance parameters using ETAS/INCA tools.

Developing Automation scripts to validate various features in Transmission system.

Evaluating project change impacts, review the required documentation in relation to the change requests, pin out diagrams, signal database for the software, highlighting risks and ensuring project objectives are met.

Running test vectors on d-Space simulators and logging the results.

Logging the identified anomalies and discussing with Control and system engineers for resolution.

Graduate Assistance January 2016 – May 2017

University of Bridgeport, CT

Low power secondary transition unit for signals using independent receiving transmitting memory interface using Mentor Graphics Tool.

Understanding of Memory Hierarchy, SRAM Layout designs and constraints.

Work closely with circuit design engineers to create complex Digital blocks for the high-speed VLSI circuits.

Maintaining proper design review documentation at every stage of designing.

Designing complex Digital blocks for the high-speed VLSI circuits under the supervision.

Apply commonly used concepts, practices, and procedures to resolve routine issues.

High Speed Memory Interface for Future Mobile Application

Created and Maintained proper design documentation.

Performed debug of complex silicon issues down to the transistor level.

Good understanding of CMOS Process technology, Low Power Circuit design.

Design of SRAM memory and interface.

Reviewed system requirements and components.

Maintaining proper design documentation for the project.

Client: Paccar India Technical Centre April 2015 – Dec 2015

Role: Validation Engineer

Performed In-Vehicle testing for the Electrical systems on different modules like BCM, ECM, TCM and ABS.

Supported the Vehicle test engineers by analyzing the CAN log and resolved issues on vehicles by identifying CAN messages.

Developed and modified test cases for testing various vehicle components and performing corner and negative test cases along with positive test cases.

Involved in flashing the software to the controller in the vehicle using Diagnostic Tools.

Implemented CANalyzer project with CAN configuration, design Panels and CAPL scripting.

Created the Test Document from the DRD (Design requirement Document).

Good at understanding the State Diagrams from the Test documents.

Used NI LabVIEW for recording and monitoring the CAN data.

Performed the Electrical Systems components test and filed the reports

Attended for Test procedure review meetings and helped in reviewing the documents.

Very good at looking the FMI’s (Failure Mode Indicators) using J1939 DTC Monitor.

Expertise in using the J1939 Scanner and CAN Statistics to check the bus communication and the error frames.

Hands on experience on using different layers like Data link, Vehicle application layer and Application layer in J1939 OSI model.

Used CAN IG (Integrative Generator) Block for Transmitting the CAN messages using the PGN (parameter Group Numbers) and SPN (Suspect Group Numbers).

Client: Defense Organization (DRDO), India May 2014 – Aug2014

Role: Internship

Dealt with the functioning of microcontroller, observing its communication with the sensors, ADC, V to F converters, compiled and loaded C,C++ based coding.

To control velocity, position and acceleration of a space craft/missile without getting in physical contact with the device rather controlling it from the stationary point on the earth.

Data was acquired from the space craft/missile regarding its current position, velocity and acceleration through sensors.

Verilog codes are to be developed for controlling position, velocity and acceleration parameters.

Worked closely with an e-ngineer to debug and dump C code on to the microcontroller.

Created and Maintained proper design documentation throughout the project.

Designed under the direction of designed experienced professionals.

Resolved issues with constructions with knowledge of principles.

Reviewed relevant codes and made decisions in accordance with requirements.


Master’s in electrical engineering (GPA- 3.7)


Bachelor in Electronics and Communication Engineering (GPA - 3.6)



Low power secondary transition unit for signals using independent receiving transmitting memory interface using Mentor Graphics Tool.

Developed, simulated and created the Schematics and Layout for a working 64X64 SRAM circuit using Mentor Graphics Tools.

Low Power VLSI Project- Analysis of Power Consumption for different circuit structures of CMOS Full Adders using P-spice.

8-bit comparator with type-2 logic shut down was implemented and its power analysis was done using P-spice.

Design and simulation of common source amplifier with gate drain loads using Mentor Graphics

Implementation of Current Mirror,8-bit ALU and Realizing the given complex circuit using all NANDs and all NORs and verifying it using Mentor Graphics Tool.

COMSOL Simulation of a MEMS Aluminum Bi-functional Micro mirror and Bio MEMS Three Input Split and Recombination Passive Micro mixer using COMSOL.

Design and stimulation of 4-bit ALU using Quantum-Dot Cellular Automata.



Low- power VLSI.

Micro Fabrication.


Modern Electronics.

Analog VLSI.

Digital VLSI.


Controls systems.

Analog and Digital communication.

Micro Electro Mechanical Systems.

Basic Circuit Analysis.

Global positioning system.

Embedded systems.

microprocessors & microcontroller.

computer organization and architecture.

Radar&satellite communication systems.

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