MICHAEL K. NGUYEN

**** ********** *****

San Jose, CA 95121

Phone: 408-***-****

Email:ac7c4n@r.postjobfree.com

Objective:

Seeking for a challenging Hardware Test Engineer position in the field of Electrical Engineering.

Experience:

Google

2016 – Present

Manufacturing Test

Tasks at Google:

Develop test procedures, improve testing process, improve SOPs and test fixtures to evaluate the EDVT on Google’s new products, including PCBAs and Assemblies.

Perform bench level testing and bring up engineering prototypes with new software release.

Setup complex test scenarios to maximize functional stress on hardware and components as well as research the test methodology in the most effective, efficient way possible.

Execute manufacturing test plans while documenting results and debugging issues found. Drive issue to closure and get corrective action with project team.

Interact with cross-functional teams for technical issues and address challenging problems.

Present status and reports of all the root causes and evaluate technical readiness prior testing at CMs.

Familiar with Python, execute, modify and debug manufacturing test cases in Python.

Familiar with firmware test, firmware updated and flashing firmware for test station and test devices.

Write bash scripts in Linux environment to control hardware for our test stations.

Work together with Vendors/CMs to build our products, provide training, technical expertise and leadership from beginning to end.

Collaborate with the design team, along with software, mechanical and manufacturing team to determine test requirements to establish test methodology and test fixture implementation. As well as characterization, maintenance, debug and deployment to CMs.

Support many test stations at multiple contract manufacturing (CM) test sites, work with CMs to prioritize and solve problems, together with them to build our boards/systems, provide technical discipline and leadership throughout the product life cycle as well as root cause the technical issues, analyze the test data and file bugs.

CISCO SYSTEMS, Inc

1999 – 2015 (15 years)

Hardware Engineer

Tasks at Cisco System, Inc:

leading a test team for 8 years to support multiple products. Also, create and standardize test procedures, test methodologies and provide supports to the teams in San Jose, china, India, Thailand and Austin, Texas as well as helping them with technical issues.

Work on analog front-end for Cisco’s switches, that’s including 10BaseT, 100BaseTx, 1000BaseT, 2.5G/5G/10G copper, Serdes, XAUI, 10G BaseT, USB2.0 and USB3.0.

I have many years of experience working on Optical interfaces. Such as XENPAK, SR, LX, LR, ER, SFP, SFP+, QSFP+ form factors. I was responsible for all the parametric testing to qualify these optical transceivers such as Bit-rates, Q-factor, Extinction ratio, Eye mask, Tx output, Jitters, Power, Distortion, BER, etc.

Responsible for all IEEE data measurements including signal transmission properties, EMI measurements, EDVT, MDVT such as corner testing, vibration, shock, humidity, Impedance Balance testing, Arc fault detection and location and circuit design.

Support the functional and system test for Multi-Gig Switches and router Network products.

Work with the Phy’s vendors (transceivers), magnetic vendors and power supply vendors to select the best components to build our products.

Perform IEEE 802.3 testing on the vendors’ silicon as early state before having these components implemented on our design. Schematic capture and PCB.

Build a test board with 48 ports simulation to emphasize the CDE (cable discharge event) design on the components.

Perform Failure Analysis, investigate the issues and responsible for set up system configuration in order to reproduce customer failure symptoms.

Identify and analyze the root cause of defective component and communicate information with customer for failure analysis and drive for defect prevention.

Create and execute detailed test script using TCL language to perform EDVT for our L2/L3 switches and routers.

Setup test equipment and support Functional test, System test, EDVT, Phy Qualification and Burn-In test for all cisco’s switches in China, Thailand, India, Austin, Texas and San Jose.

I also have performed front-end test base on IEEE 802.3 standard to test optical 3.125bps, 10.3125bps as well as XAUI and Serdes.

Responsible for all analog front-end design and test included Functional, system burn-in chamber, HALT, HASS, MDVT, EDVT, Phy Qual, CDE, cable discharge event, Hipot, ESD, EMI Compliance, Power Test, WIFI and mechanical.

Perform weekly/annually maintenance and calibrate all the test equipment.

Use firmware diagnostic to narrow down to the location for easy to debug and identify the problems such as defect components or process defect.

Technical:

Python, lab view, TCL, Linux, UNIX. Cisco Switches, Routers.

Lab equipment: Real-time and sampling Oscilloscopes, Frequency Generator/ Counter, Function Generators, Network Analyzer, 3D X-ray machine, BERTs Scope. Spectrum analyzer, VNA, TDR.

Education:

Bachelor of Electrical Engineering from San Jose State University

December 99.

Reference:

Available upon request.

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