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Design Electrical Engineering

Cincinnati, Ohio, United States
January 17, 2019

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• Master of Engineering in Electrical Engineering GPA: 3.69 University of Cincinnati, College of Engineering and Applied Science, Cincinnati, OH Aug 2017 – Present Relevant Courses: Introduction to VLSI, VLSI Design Automation, VLSI Test and Low Power, Topics in VLSI CAD, Embedded System, Advanced Algorithm

• Bachelor of Engineering in Electronics and Telecommunication GPA: 3.7 University of Mumbai Aug 2011 – Jun 2014

Relevant Courses: Microelectronics, Digital Logic Design, Digital Signal Processing, Microprocessor and Microcontroller, Wireless Communication


• Hardware Description Language: Verilog, System Verilog, UVM, VHDL

• Scripting Language: Python Scripting, Perl, TCL, MATLAB

• Programming Language: C, C++, Embedded C, Assembly Language, JAVA

• EDA Tools: Synopsys Design Compiler, TetraMax, HSpice, IRSIM, Altera Quartus Prime, Magic, Mentor Graphics Modelsim

• Operating Systems: Windows, Mac, Linux, Ubuntu


• Design of Alpha Architecture Pipelined Microprocessor with Hazard Detection, Branch Prediction and Forwarding Unit Designed a 5-stage pipelined microprocessor using System Verilog for Hazard Detection, Branch Prediction and Forwarding Unit to increase the Clock Per Instruction (CPI) of the system and simulated the design using Synopsys VCS. Wrote Perl Scripts to convert the soft codes into Alpha64 compatible assembly language and in turn into the machine code to run different testcases using I/O file operations in Verilog.

• Verification of AXI Interconnect

Simulated the behavior of AXI-4 using UVM methodology and System Verilog. Validated various features like data burst, multiple outstanding transactions on Synopsys VCS. Built different UVM DV agents like Scoreboard, Drivers, Monitors.

• Cell Placement and Cell Routing for 1000 netlists Implemented placement of cell using Force Directed Algorithm and data structures like map, vector, and vector of vectors were used. Performed channel routing using unconstrained and constrained left edge algorithm.

• Boundary Scan and ATPG on a Greatest Common Divisor (GCD) circuit using 90nm CMOS Technology Designed a GCD circuit in VHDL and Verilog along with a Test Access Port (TAP) controller that controls the internal and boundary scan design using 4 pins (Test Data Input, Test Data Output, Test Mode Select and Test Clock Input). Internal scan and boundary scan chains were stitched together with the help of TCL commands and its functionality was tested in Synopsys Design Compiler.

• KL Algorithm for cell partitioning of 100**-****** benchmark netlists Developed a C++ code to execute cell partitioning algorithm of a complexity of O(n2).

• DFT and ATPG on a Square Root Calculator using 90nm CMOS Technology RTL design of a Square Root circuit is implemented using Verilog and synthesis using Synopsys Design Compiler. Inserted the scan chain in the design and tested it using ATPG with the help of TetraMax tool.

• 24-bits String Matching using 0.5u CMOS Technology Constructed the RTL hardware implementation of a String-Matching circuit using VHDL and verified it. Accomplished placement and routing manually using Magic Tool and standard libraries. Used HSpice and IRSIM to test the performance of the design which lead to generation .cif file.

• Analysis of Approximate Multiplier

Described RTL of an approximate multiplier using Verilog and its performance was compared against the standard Wallace Tree Multiplier. Performance factors included accuracy, power and critical path along with slack. Synthesis and power dissipation analysis of 16-bit and 32-bit multipliers was carried out using Design Compiler. PREVIOUS EMPLOYMENT:

Web Application and UI Developer

Tata Consultancy Services Ltd Oct 2014 – Jun 2017

• Designed responsive and interactive web pages using HTML5, CSS, jQuery, JavaScript. Catered enhancement request in Drupal 7. Implementation of Omniture Tracking. Maintained version control using GitHub tools.

• Hands-on experience with tools like Zendesk and Jira for accurate request exchange. Interaction with clients for knowledge transition on implemented enhanced features. Mentored juniors, imparted knowledge on the process and handling request.

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