POOJA KALE

408-***-**** ac75kn@r.postjobfree.com https://github.com/pkale

Education CORNELL UNIVERSITY New York,

Master of Engineering in Computer Science, May 2019, Merit Scholar NY PURDUE UNIVERSITY Lafayette,

Skills

Bachelor of Engineering in Computer Engineering, 2017, Presidential Scholar Purdue Pathmaker’s Program, Co-op student with Hewlett Packard Programming Languages: Python, Java, C++, C, JavaScript, C#, Verilog, Assembly Tools & Libraries: Jupyter Notebooks, Google Collaboratory, Django, Flask, Unity, XCode Pandas, Scikit-Learn, Apple’s ARKit, PostgreSQL, REST, D3 IN

Projects

Current

Applied Machine Learning, Cornell

• Designed a Facial Recognition system with SVD for image reconstruction

• Developed a Sentimental Analysis Tool for online reviews with Bag of Words model, implemented PCA to reduce feature dimensions & clustering for text analysis

• Developed a Hand-Written Digit Recognizer with 96.7% accuracy (Kaggle) using self- designed k-Nearest Neighbor classifier & 3-fold cross validation

• Other Kaggle Competitions: Titanic (78% Acc.), What’s Cooking? (78.3% Acc.)

(ICO) Initial Coin Offering Financial Tracking Framework, Cornell Startup Studio Prototype: www.vestvault.com

• Developed a smart-contract generator that enforces the pre-ICO launch token distribution model presented by the client company, in a secure and transparent way

• Maintained client input data with PostgreSQL Rest APIs and visualized token distribution model with D3, on a Django web framework

• Developed on Ethereum Blockchain using Solidity to track Cryptocurrency transactions Compiler, Purdue Compilers

• Created a full scale compiler in Java, using Antlr to compile LITTLE programming language

• Implemented a complete register allocation assuming a 4-register, register file on processor

• Generated assembly for if-else constructs, for & do-while loops, complex mathematical expressions, and recursive calls handling all data type variables.

(CPU) Dual Core Processor, Purdue Computer Architecture

• Designed and implemented an L2 Cache Multicore Processor. Coded(Verilog) a single cycle implementation, data streamed pipelined CPU, and I-cache & D-cache hierarchy for memory HEWLETT PACKARD ENTERPRISE

HPE Aruba Wireless Optimizing Features Team, Embedded Design Engineer Intern

• Contributed to Aruba AirMatch, an RF optimization technology to automate Wi-Fi-networks for higher performance on wireless (APs) Access Points or router embedded systems

• Enhanced 25+ existing features across AirMatch software that optimize EIRP (TX Power), channel & channel bandwidth assignment for B2B enterprise router plans

• Designed a new multi threaded feature to track large scale DB-dump of optimization graphs HPE Core 8400 Switch Operating System Team, Software Engineer Intern

• Created a data visualization web framework, to navigate unstructured data folder of Aruba Switch features, currently utilized by 300+ developers

• Developed the navigator, using Flask Python framework with D3 for frontend HPE Labs, (SDN) Software Defined Networking Team, Software Engineer Intern

• Developed a support UX framework to help customers configure the SDN controller

• Created an interactive interface for users to access a personalized configuration guide for deploying the SDN controller, leveraging Java Spring MVC framework New York,

NY

Current

2017

Lafayette,

IN

2017

Experience

2018

2016-2017

2015

Palo Alto,

CA