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Design Engineering

Location:
Montreal, Quebec, Canada
Posted:
September 10, 2018

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Resume:

ANKIT DAVE

**** ********* ** *********** *****, Apartment 508, Montreal, QC, Canada - H3H 1L2.

438-***-**** ac6zyt@r.postjobfree.com

https://www.linkedin.com/in/ankit-dave-353bb3a3/

PROFESSIONAL SUMMARY

Ambitious entry-level hardware design and verification engineer with a strong desire to apply education for root cause analysis. Committed and diverse with the ability to work with all types of personalities. Experienced with system design using VHDL and Verilog and system verification using System Verilog. Looking for an opportunity to work with a cutting-edge technology and services organization. SKILLS

Languages: C, C++, Assembly Language, VHDL,

System Verilog and UML.

Software: Cadence Conformal, Synopsys Formality, Modelsim, Xilinx ISE, CISCO Packet

Tracer, Qualnet, Proteus, Arduino, mbed.

Hardware design

Knowledge of circuit boards, electronic apparatus and equipment

Programming a microprocessor and microcontroller

Team leadership

Debugging proficiency

Project management

Advanced critical thinking

Excellent communication skills

Project documentation

Excellent problem-solving abilities

Windows and Linux

EDUCATION

Master of Engineering: Electrical and Computer Engineering, 2018 Concordia University, Montreal, QC

Graduated with 3.52 GPA

Majored in ASIC Design and Verification, Computer Engineering and Communication Engineering.

Coursework in Digital system design, Computer architecture and design, Microprocessor and their applications, Formal hardware verification and Functional hardware verification. Bachelor of Engineering: Electronics and Communication Engineering, 2015 Gujarat Technological University, Ahmedabad, India

Graduated with 7.92 GPA

Majored in Embedded and VLSI technology.

WORK HISTORY

Service desk operator, 05/2017 to 05/2018

Concordia University - Montreal, QC

First line of contact for IT related issues throughout the Engineering and Computer Science Department.

Resolving or escalating the issue to the concerned team as per requirement. Teaching Assistant, 09/2017 to 12/2017

Concordia University - Montreal, QC

Taught basic practical concepts of digital design (building adders and multipliers on breadboards and their debugging to undergraduate students for COEN212 at Concordia University, Montreal. RELEVENT COURSEWORK AND PROJECTS

Digital system design:

Introduction to Digital Design process for combinational as well as sequential circuits.

Modelling digital circuits using VHDL.

Synthesis of Digital circuits using CAD tools.

Designed a 16-bit Adder using VHDL in Modelsim.

Synthesized the adder using Xilinx ISE.

Computer Architecture and Design:

Understanding the hardware design issues of high performance computer architectures.

Instruction pipelining and hazards, Memory hierarchy, Parallelism.

Design a simple pipeline processor, Mini-MIPS, which is a subset of the 32-bit MIPS architecture.

Design made at RTL level using VHDL, avoiding pipelining hazards. Tested for any bugs. Microprocessor and their applications:

Introduction to microprocessors and their architectures.

Bus and I/O Organizations. Addressing modes.

Timing, Software related issues, Memory and its hierarchy, Static and dynamic memory interfacing, Synchronous and asynchronous interfacing, Interrupts. DMA. Use of Co-processors. Single chip Micro- controllers.

Developed a Sign language translating glove, using ARM KL25Z: http://edlib.net/2015/icieca/ICIECA2015004.pdf

Formal Hardware Verification:

Synthesized an RTL design to gate level.

Compared RTL and synthesized gate level design for any synthesis error.

Gate level synthesis checked for equivalence with a provided buggy file using Synopsys Formality and Cadence Conformal Logic Equivalence Checker to find bugs and correct them. Functional Hardware Verification:

Introduction to hardware verification practices in the industry and its importance.

Verification of three calculator design specifications provided by IBM.

Building test cases, test plan, and a smart re-usable environment using system verilog.

Generated bug report and functional coverage report for each DUT.



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