Design Security

Nandeesha Veeranna

*.********@*****.*** (**) ****8565 https://www.linkedin.com/in/nandeeshv

Nanyang Technological University, School of Computer Science and Engineering, Hardware & Embedded Systems Lab, N4-B2b-05, 50 Nanyang Avenue, Singapore 639798

Summary

Recent PhD graduate with over four years of research experience in High-Level Synthesis (HLS), RTL design, debugging and verification, hardware security, optimization and Reconfigurable Computing. Over two years of industry experience in verification and validation of semiconductor IPs. A capable professional believing in hard work and willing to take challenges in science and technology.

Education

PhD in Electronic and Information Engineering July 2014 - Nov 2017 The Hong Kong Polytechnic University, Kowloon, Hong Kong Thesis:Design for Trust in Behavioral VLSI Design. gpa 4.0/4 This thesis investigated the types of hardware Trojans in behavioral intellectual properties (BIPs) and proposed techniques to detect the hardware Trojans in BIPs and behavioral MPSoCs. This thesis also proposed a technique to obfuscate the BIPs for HLS efficiently. The major contributions of this thesis are summarized as follows:

Developed an open source benchmark suite of synthesizable behavioral descriptions with different types of hardware Trojans which are difficult to detect using typical software profiler.

Introduced a fully automatic method to detect the presence of hardware Trojans in third- party BIPs (3PBIPs) using formal verification methods. In particular, property checking at the behavioral level.

Introduced a run-time system level method to detect hardware Trojans in behavioral multi-processor systems.

Proposed a mechanism to detect and avoid the hardware Trojan being triggered in run-time reconfigurable field programmable gate arrays (FPGAs) in particular, coarse-grained run-time reconfigurable array (CGRRA).

Studied the impact of source code obfuscation on the quality of results of BIPs for HLS and proposed a quick and efficient method to maximize the source code obfuscation while preserving the original design characteristics. Masters in VLSI design and Embedded Systems Sep 2011 - Aug 2013 RV College of Engineering, Bangalore, India gpa 81.07% Thesis: Design and Development of Simulation Interface Tool for Automatic Testcase Generation and RTL Debug. In the conventional verification flow, the targeted VHDL verification is done prior/parallel to Specmen/e verification to test the basic functionality of the design which introduces the high effort of developing VHDL verification testbench before it is handover for Specman verification. The proposed approach tries to minimize the parallel effort by developing an interface tool which can be easily used by the designers. Bachelor of Engineering in Electronics & Communication Sep 2006 - June 2010 Siddaganga Institute of Technology, Tumkur, India gpa 82.33% Skills

Algorithm verification using C, C++, Python. Scripting using Perl, Shell.

RTL coding in Verilog HDL, VHDL. SystemC for modelling

Tools: Modelsim and NC-sim for functional simulation, Cyberworkbench and Vivado HLS for High-Level Synthesis, Xilinx ISE and Altera for FPGA design, Specman for verification.

OS: Windows, Linux.

Professional Experience

Research Fellow, Nanyang Technological University, Singapore Sep 2017 - present Worked on the project ”Multi-Objective optimization of program obfuscation using Genetic Algorithm”.

– Developed a framework to optimize the obfuscation process from three different angles, i.e., performance, obscurity, and side-channel security.

– Targeted RISC-V architecture, an open source ISA to validate our approach which includes Rocket core processor, a custom defined Rocket Chip Co-Processor (RoCC).

– On the software side, clang and LLVM (with RISC-V support) compiler is used to compile the source code

(C/C and at the back-end, RISC-V ISA compatible gcc is used to generate the executable from the assembly code.

– On the hardware side, a RISC-V platform is built targeting Zedboard that contains the Zynq-7000 XC7Z020- CLG484-1 FPGA device.

Visiting Research Scholar, University of Texas at Dallas Apr 2017 - July 2017

– Worked on a funded project ”Efficient Behavioral IP source code obfuscation for High-level Synthesis”.

– Took part in a hardware security contest, HACK@DAC held at 54th Design Automation Conference (DAC), Austin, USA, 22-27 June, 2017.

Graduate Teaching Assistant, The Hong Kong Polytechnic University Jan 2015 - Jan 2017 Teaching assistant during PhD for the courses VLSI System Design (EIE511), VLSI CAD (EIE 411), Mobile Computer System Architecture (EIE4103).

Verification and Validation Engineer, Infineon Technologies India Pvt.Ltd, Bangalore, India Aug 2013 - June 2014 Responsible for validation of I2C and ASCLIN communication protocols.

Intern, Infineon Technologies India Pvt.Ltd, Bangalore, India Aug 2012 - July 2013 Masters Dissertation, “Design and Development of Simulation Interface Tool for Automatic Testcase Generation and RTL Debug”. This project aims at developing a simulation interface tool for auto testcase generation in the verification platform.

Publications

N. Veeranna, B. Schafer, “S3CBench: Synthesizable Security SystemC Benchmarks for High-level Synthesis,” Journal of Hardware and System Security, Springer, July 2017, doi:10.1007/s41635-017-0014-1.

N. Veeranna, B. Carrion Schafer, “Automatic Hardware Trojan insertion in Behavioral IPs during the Obfuscation Process,” won the third prize in HACK@DAC Hardware Security contest in Design Automation Conference (DAC), Austin, USA, 2017, poster.

N. Veeranna B. Schafer, “Trust Filter: Run-time Hardware Trojan Detection in Behavioral MPSoCs,” Journal of Hardware and System Security, Springer, April 2017, doi:10.1007/s41635-017-0005-2.

N. Veeranna, B. Schafer, “Efficient Behavioral Intellectual Properties Source Code Obfuscation for High-Level Synthesis,” in IEEE Latin American Test Symposium (LATS), Bogota, Columbia, 13-15 March, 2017.

N. Veeranna, B. Schafer, “Hardware Trojan Avoidance and Detection for Dynamically Re-configurable FPGAs,” IEEE International Conference on Field Programmable Technology (FPT), Xi’an, China, 7-10 December, 2016.

A. Balachandran, N. Veeranna, B. Schafer, “On Time Redundancy of Fault Tolerant C-Based MPSoCs,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, Pennsylvania, 11-13 July 2016.

N. Veeranna, B. Schafer, “Hardware Trojan detection in Behavioral Intellectual Properties (IPs) using Property Checking Techniques,” IEEE Transactions on Emerging Topics in Computing, Volume 5,issue 4, June 2016.

T.Pham, A. Biswas, A. Fell, S.K. Lam, N. Veeranna “CIDPro: Custom Instructions for Dynamic Program Diversifica- tion,” Accepted for Publication in International Conference on Field Programmable Logic (FPL), Dublin, Ireland, 27-31 August 2018.

N. Veeranna, A. Biswas, T.Pham, A. Fell, S.K. Lam “Multi-Objective Optimization of Program Obfuscation using Genetic Algorithm,” Submitted to IEEE Transactions on Emerging Topics in Computing. Awards and Achievements

Obtained scholarship from Hong Kong government to pursue PhD in The Hong Kong Polytechnic University.

Best poster design award in poster design contest held in the Department of Electronic and Information Engineering at The Hong Kong Polytechnic University (PolyU), April 2015.

Won the third prize in HACK@DAC Hardware Security contest in Design Automation Conference (DAC), Austin, USA, June 2017.

Finalist in HACK@DAC Hardware Security contest in Design Automation Conference (DAC), San Francisco, USA, June 2018.

Hobbies and Extracurricular Activities

Semipro cuber - Developed my own customized Algorithm to solve 4x4x4, 5x5x5, 6x6x6, 7x7x7 Rubik cubes from the existing 3x3x3 Algorithm.

Marathon runner, semipro badminton player, long distance swimmer.

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