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Mask Design Engineer

Location:
Mountain View, California, United States
Posted:
August 29, 2018

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Resume:

Steven E. Grubb

**** ****** ****

Mountain View, CA 94040

650-***-**** (M)

650-***-**** (H)

ac6u0p@r.postjobfree.com

CARREER SUMMARY MASK DESIGN SPECIALIST ONLY/NOT AN EE

> Profession experience includes over thirty (30+) years of integrated circuit mask design experience, over twenty-five

(25+) years of experience utilizing twelve (12) different CAD systems, and over twenty (+20) years of project lead

experience with top-level verification integration, as well as project and schedule management.

> Block level and top-level floor planning with engineering staff. Layout overview for Low/Hi Power and

grid routing, EM, and clock path check.

> FinFet processes Intel 22nm, Nvidia TSMC 16nm, IBM/Global Foundries 14nm, and just recently got

my feet wet with Intel s 10nm process (difficult to say the least)

> Other Processes utilized include IBM 140nm SOI, 120nm, 90nm, 65nm, Chartered 45nm, TSMC 40nm at Ambiq Micro, and TSMC 28nm,

Fujitsu 28nm, G.F .28nm, IBM 28nm, Samsung 28nm.

> Analog and RF, areas: PLL s, voltage regulators, power amps, opamps, oscillators, comparators, bias distribution, and the

RF considerations that go with these circuits, such as Signal Isolation, Bias/Ground Plane Decoupling. Bandgap, LDO, LNA,

ADC/DAC, RX/TX, VCO s, LO supply gens. Two SERDES Projects.

> Digital Libraries built: two at Micron and a high performance digital cell library for Tabula s High speed SERDES project.

> Memories worked on and with: Mostec > DRAMS to Catalyst Semiconductor > NVRAMS, EPROMS, PEROMS and NOR Flash to

Micron > NOR and NAND Flash Memory Products, SRAM s for R&D at Nvidia, and Ambiq Micro (super low power) and an SSM part

for IBM going to cloud computing, several small imbedded SRAM s and 3 different image sensors for QUSEMDE and Foveon, and

more Cloud Computing Application s with Rambus Cold Process (next to last Job).

> Differential Signaling, Common Centroid devices, Device Matching, Cross Coupling Considerations and High Power Aplications .

> I/O building experience includes ESD structures, interior and exterior substrate and well-shielding, including I/O pads,

RB pads, data I/O pads, VCC, GND, V5, V10, V20 pads, output pads, bump pads and Scribe Grid area test circuits along with

chip tape-out considerations through to final tape out

> Layout programs used include DRC/LVS/ERC/ANT/DFM with the following programs:

Cadence 12.1, Virtuoso (VXL), Diva, Hercules, Calibre, Assura, Mentor Graphics, PVC

Have used Cadence Place & Route tools, as well as Synopsis Library Management

PROFESSIONAL EXPERIENCE

Currently - Not Working (Just Finished rebuilding our Master Bathroom 12 weeks start to finish. Complete tear down, Walls, Floor,

Plumbing and Electric.)

Feb.18, 2018-May 25, 2018 CIENA of Canada

Senior Analog Mask Designer (Contract Employee for Synapse)

I rebuilt an ADC_DAC_Filter and all of the subcells complete through Tape-Out. Harry Peterson, MGR.

Sept.11, 2017 Feb.15,2018 RAMBUS, Sunnyvale

Senior Analog Mask Designer (Contract Employee for Synapse)

We put together a Test Vehicle in 28 nm. for Rambus Glider Project, Cryonic Analog for Samsung

Cadence platform 6.1.5 with Calibre checking tools and PDK available. Carl Werner. MGR.

Apr 12, 2017 Jun 31 2017 INTEL Santa Clara

Senior Analog Mask Designer (Contract Employee for Synapse)

We put together a Test Vehicle in 10 nm. Built 1 of 4 DUT s for Cloud Computing 50Ghz Analog

Cadence platform 6.1.5 with Calibre checking tools and no procedures available. Dan Burres MGR

July 12 2016 Jan 31 2017 ASIC North, Tempe, Arizona

Senior Analog Mask Engineer (Contract Employee)

We put together a Pad Ring I/O project for a small image sensor group (Foveon).

I helped construct two Standard Cell Libraries and built a Differential Comparator and Diff Pre-Amp for

for a government project, this was in 40nm SOI technology.

Cadence platform 6.1.5 with Calibre checking tools and have written up three different procedures.

Worked on a third project, a High Power Diff Amplifier for IOT: ASIC North proprietary. Jeff Norvig MGR.

Oct. 5 2015 December 30 2015 Ambiq Micro, San Jose

Senior Mixed Signal Mask Engineer (Contract)

Was on this job for 3 months and working with a former Manager that asked if I had a couple of

months available, This was Christophe Chevallier

We built a very low power part (test vehicle) for Ambiq that will be going out the door when we

finish, as we are adding another version SRAM to the existing part.

Cadence platform 6.1.5 and PVC checking tool for DRC/LVS/ANT using a 40nm TSMC process

Apr. 2015 September 30, 2015 IBM/Global Foundries working for EncoreSemi, Vermont and Home

Senior Mixed Signal Mask Engineer (Contract)

Built a low power SSM for IBM future use in Laptops and Tablets and Cloud Environment.

We were building the Non-Core Essential Analog and Digital Blocks, The controlling elements of part:

RW and Hold Clock Delays, Adders, Controllers, A/RIOSFC(SysFileChecker), Mostly Digital elements

for this part, utilizing Matching and Node sharing through to DRC/LVS Clean.

Virtuoso 12.1 with Calibre DRC and ICV LVS. Nice 14nm IBM DP Coloring Process

Older Data

Apr 2014 Jan 2015 Foveon Inc. (Division of Sigma), Santa Clara, CA

Senior Analog Mask Engineer (Contract)

Built a low power image sensor in a new aspect ratio for a new Sigma camera

Built the Analog sections with interface to the Digital Blocks, (Mixed Signal) and the entire Pixel Core.

Built VReg clamps, clock gens, LatComp, pixel/BitArray, and all three (3) major macro corners on Synopsis Platform

with Calibre as a checking tool for DRC/LVS/ANT using a 120nm process

Feb 2014 March 2014 Synapse Design, Santa Clara, CA

Senior Mixed Signal Mask Engineer (Contract)

Started and completed another SerDes project using RF peripheral I/O considerations, with several SRAMs attached

for a customer of Synapse Design Cadence/Calibre on 55nm process

June 2013 Sept 2013 NVIDIA, Santa Clara, CA

Senior Mixed Signal Memory Mask Engineer (Contract)

Started and completed a SRAM test vehicle for R&D group

Built the IO-write block and interfaced the read decode

This was a tile type design using high-end device matching and common centroid configurations.

Developed all of the top and block level floor planning with engineer, and routing through to tapeout preparation

Cadence 6.1.5 Calibre Utilities used for DRC/LVS/ERC/ANT 16nm TSMC Process

April 2013 June 2013 NXP (Phillips), San Jose, CA

Senior Analog Mask Engineer (Contract)

Assisted with SOI 140nm IBM Process mixed-signal and RF bias and Ground plane stressed high and low voltage applications.

In charge of top-level planning, place & routing through to tapeout. Cadence design W/ PVC checks

Oct 2012 March 2013 CrestaTech, Inc., Santa Clara, CA

Senior Analog Mask Engineer (Contract)

Helped start-up with the SRAM support features and analog portion with RF considerations for this TV Part including

an oscillator, comparators, amp control, LDO, LNA, 65nm TSMC Process @ 25GHz using Cadence with PVC checks

Aug 2011 Oct 2012 Tabula, Santa Clara, CA

Senior Analog Mask Engineer (Contract)

Worked on SerDes part; mixed-signal and analog blocks, voltage regulators, PLL clock buffers and dividers Rx analog

front-end BIAS in serial IO section of circuit

Built a high performance digital cell library to interface with analog blocks

Lots of voltage shifting up and down voltage levels, using level shifters, opamps, and comparators

Power amps, phase detectors, resistor matching, charge pumps, local supply, gens, and guard rings everywhere

Used Cadence 6.1.5 with Hercules DRC/ERC/LVS/ERC/ANT on 22nm Intel Process @ 25GHz

Continued learning SKILL

Aug 2010 July 2011 LSI Corporation, Milpitas, CA

Senior Analog Layout Design Engineer (Contract)

Built SerDes layouts

Worked on PLL feedback clock select and counter, ripple counter, AFE Offset1V, RX_AFE_V0, Muxbuffs, PLL, and

a power ground sensor; enhanced some of the IO protection devices

Used Cadence 6.1.4.5 with Calibre DRC/LVS/ERC/ANT/GDR 28nm TSMC Process @ 50GHz

Started learning SKILL

Aug 2009 Aug 2010 Global Foundries, AMD Sunnyvale, CA

Senior Analog Layout Designer (Contract)

Built analog blocks, integer block, feedback divider, PLL control, ESD, ADC/DAC diode clamp and I/O pad structs

to tapeout

Worked on digital library building standard cells

Cadence 6.1.4 using Calibre s DRC, LVS, ERC, DFM 28nm Chartered Process @ 50GHz

Feb 2008 July 2009 Fujitsu Labs America, Sunnyvale, CA

Senior Mixed Signal Layout Designer (Contract)

Built RF analog blocks for R/D test vehicles opamps, power clamps, decoders, relays, baseband filtering,

bandgap filters and LDO block

Cadence 6.1.1, used Calibre s DRC, LVS, ERC, GDR, ANT rules, Fujitsu s 45nm Process @ 10GHz.

Sept 2007 Jan 2008 Qualcomm, Santa Clara, CA

Senior Layout Designer (Contract)

Built RF analog blocks, lev-shifter, VCO, oscillator, voltage regulator and control logic (mixed-signal),

1.3V operational transconductor amp, and inductor

Cadence, 65nm TSMC Process @ 5 GHz

Oct 1996 July 2007 Micron Technology Inc., San Jose, CA

Senior Layout Design Engineer

Completed extensive work on NOR and NAND flash memory products passing through Micron ten (10) years

Led the design of ten (10) products during this period, from 64Mg parts to 8Gb products

March 1990 July 1996 Catalyst Semiconductor Inc., Santa Clara, CA

Senior Layout Designer (Contract)

Built a 1Mg PEROM and 64K, 16K, 4K, 2K, and 1K EEPROMs with onboard RF analog blocks, and a 1K to 256-bit

family of NVRAMS

Product line EPROMs, EEPROMs and non-volatile parts

Acquired extensive knowledge of and experience with Daisy and Cadence system

Nov 1989 March 1990 Elantec, Milpitas, CA

Senior Layout Designer (Contract)

Built an ADC in Junction Isolation Bipolar High Voltage using a Valid system

Dec 1988 Nov 1989 Fujitsu Microelectronics Inc., San Jose, CA

Senior Layout Designer (Contract through IC Design Shop)

Managed assembling of a register file part for SPARC on a SUN 4 terminal utilizing Cadence software

Performed additional work involved building standard cells

March 1988 Dec 1988 Delco Electronics, Kokomo, IN

Senior Layout Designer (Contract with Richard Reel)

Duties included 50% of all major planning and routing for TIO project

Performed work on an 80K device microprocessor-based engine controller at 3 microns CMOS, on-line Calma

Jan 1988 Feb 988 AMD, Austin, TX

Senior Layout Designer (Contractor with Austek)

Managed 50% of all major planning and routing for the 8530 on-the-board layout

Jan 1987 Dec 1987 AMD, Austin, TX

Senior Layout Designer (Contractor with Austek)

Called in at end of contract to help with routing for AM29C327

Aug 1985 Sept 1987 Crystal Semiconductor, Austin, TX

Senior Layout Designer

Performed on-line design using in-house Unix Graphics-VAX system for configuration

Headed layout designer on T1-transceiver and provision of ongoing support for 5316 Delta-Sigma and 5212 two-step flash

Worked with analog-digital Mixed Signal 3 micron Si-Gate CMOS processes and High and Low Voltage applicaions.

EDUCATION & OTHER TRAINING

AA, Social Psychology, Foothill College, San Francisco, CA

Liberal Arts Studies, San Jose State University, CA

Certificate in Mask Layout Design, Certification Program, Maness LSI Design, CA

CMOS Layout Design Course for Cadence VXL

Microsoft classes for Word and Excel

Taught CMOS layout to junior designers and have led teams of both junior and senior designers from chip planning through tape out



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