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Power Design

Fairborn, Ohio, United States
August 15, 2018

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* * * * *

Gitesh Kumar Ghanghorkar

**** ***** **** ******, *** #102,

Fairborn, Ohio 45324


Phone no: +1-937-***-****


To obtain a position that will enable me to utilize my strong organizational, analytical and design skills along with strong educational background, and ability to work well with people. EDUCATION:

Master of Science in electrical engineering.

Wright State University

GPA: 3.36/4.0

Apr 2018

Dayton, OH, USA

Bachelor of Engineering in Electronics

and Telecommunication.

RTMNU Nagpur university


Dec 2013

Nagpur, MH, INDIA


• Verilog.


• VLSI layout designing

on Cadence virtuoso.

• RTL Designing

• PLC automation.

• Ladder-logic


• Power circuit designing

on Saber.


• Digital IC design with

PLD’s and FPGA.

• VLSI circuit design.

• low power VLSI system


• Embedded systems.

• Trust in IC designing.

• automation robotics.

• Industrial controls and


• RF power amplifier.

• Power electronics.


• Cadence virtuoso.

• Python


• Quartus prime.

• Hspice Synopsys.

• Saber.


• C programming.

• Logixpro500.

• Rslogix5000.

• Microsoft Word.

• Microsoft Excel.

• Microsoft PowerPoint


Industrial Training.

Regional Telecom Training Center● Nagpur, Maharashtra January 2014 – June 2014

• Learnt the process of communication in wired and wireless network.

• Learnt about the evolution of 2G,3G,4G and how it works.

• Learnt Optimization, Network operation center, RF module, Wireless networks, Data Communication, GSM, CDMA, WCDMA, HSPA, LTE and migration to 4G.

2 P a g e

Gitesh Kumar Ghanghorkar


7-bit Asynchronous Multiplier on FPGA. November 2017 - December 2017

• Designed a circuit that multiplies two 7-bit binary numbers using threshold gates.

• Designed the multiplier using the VHDL language on Xilinx.

• Learnt how to dump code from Xilinx to FPGA board wherein the 16x2 LCD display shows the 7-bit multiplication result.

Layout design of 8-bit ALU using 250 nm technology. October 2016 - December 2016

• Designed the layout of an 8-bit ALU on cadence virtuoso using 180 nm technology.

• Achieved the ALU design layout area Dimension of 242.64nm by 92.16nm.

• Performed the different Arithmetic operation such as multiplication, division, addition, subtraction using the layout design and got perfect results.

Low-power Square-Root Carry Select Adder. February 2017- March 2017

• Designed a low power square root carry select adder using TSMC 0.25μm technology on cadence virtuoso design tool.

• Implemented efficient modification on the conventional square root CSA to reduce its Area and Power.

• Got fully functional Square root carry select adder designed having low Power consumption. Low-power Decomposition Multiplier (8x8 bit) using Complementary Pass-Transistor Logic Carry Select Adder. March 2017- April 2017

• Designed low-power Decomposition multiplier using TSMC 0.25μm technology on cadence virtuoso design tool.

• Achieved to keep the propagation delay as low as possible to ensure fast working circuit in terms of Delay.

• Obtained a low power dissipating design of 8x8 Decomposition multiplier. PLC Automation Project Tasks: March 2018 – April 2018 a. Sensor Circuit for a Heat-treating Unit.

• Designed Ladder Program in RSlogix 5000 for the circuit.

• Learnt how to simulate the program in RSlogix 5000 and to dump it on PLC Module(Allen- Bradley).

• Implemented comparator circuit in the design to get the desired output depending upon the input given by the Thermocouple to the PLC.

• Learnt how to use Proximity sensor with PLC module to count the number of parts entering or leaving the Unit.

• Learnt how to use the Thermocouple to sense the Heat inside the Unit. Stack light (red, amber, green) was used to represent the Heat inside the Unit. b. Traffic Light Simulation:

• Considering the real-time scenario, designed a full functional Ladder logic program in RSlogix- 5000 and implemented it on the PLC module. Used stack lights to indicate red, amber, green signals.

c. Multi-Floor Elevator Simulation:

• Developed a ladder program for the multi-floor elevator in Logix-pro 500.

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