Engineer Design

SUNIL M. SAHOO

**** ******* ***** ************, ** 78660

Email: ***********@*****.*** Phone: 215-***-****

SUMMARY

Motivated professional with 7 years of experience in the field of FPGA design and verification, knowledge of various hardware description and verification languages. Extensive experience of EDA tools and the knowhow of various design and verification methodologies. Experienced in handling onsite meeting and trainings with potential and existing customers. Excellent interpersonal skills and the ability to communicate effectively.

WORK EXPERIENCE

Applications Engineering Manager Mar 2018 – Present Aldec Inc, Henderson, NV

Manage team of AE’s, Support Engineers and Interns to efficiently handle customer issues.

Oversee projects done by AE’s and interns.

Train new interns on the tools and methodologies used.

Reviewing videos and documents created by AE’s and interns prior to uploading to the web.

Blog topics relevant to the industry used for press releases. Sr. Corporate Applications Engineer July 2013 – Mar 2018 Aldec Inc, Henderson, NV

Working with partners (Xilinx, Altera, etc) to integrate Aldec’s tools with their design flow.

Writing technical documentation such as application notes, user guides and tutorials for various tools in Aldec’s product line.

Conducting worldwide online webinars on important topics in the field of EDA. Corporate Applications Engineer August 2011 – July 2013 Aldec Inc, Henderson, NV

Assisting pre-sales engagements for Aldec’s functional verification product line by providing technical guidance to FPGA designer facing design and verification challenges.

Developing of VHDL, Verilog, System Verilog, Assertions and UVM based designs for demos.

Creating Tcl/perl scripts to automate simulation runs and benchmarking performance.

Providing technical training and demonstrations of simulation tools, language methodologies and feature to engineers online and also on-site.

Managing all aspects of the Aldec Cloud solutions for simulation on the cloud.

Handling customer designs (VHDL, Verilog, SV/UVM) to detect issues or bugs in the tools and/or the source code.

Working closely with R&D to provide solutions for customer problems. Hardware Engineer May 2009 – July 2011

InterDigital Communications LLC, King of Prussia, PA.

Worked as a hardware engineer in a company which specializes in Wireless Communications.

Participating in block level architecture design, behavioral and RTL coding for next generation cellular devices using VHDL or Verilog.

Creating testbenches and test cases for functional verification of the design using simulation.

Developing and deploying state-of-the-art RTL design

Generating flow, block and timing diagrams for detailed design documentation.

Researching various air interfaces standard’s 3GPP specifications.

Creating tests to perform channel coding in 2G, 3G, LTE, 802.11 standards.

Documenting and managing files using version control software (clearcase). TECHNICAL SKILLS

Proficient in the following Computer languages, tools and operating systems:

Working experience of VHDL, Verilog, SystemVerilog, SystemC, C/C++, Assertions, UVM/OVM, OSVVM.

Knowledge of Design and Verification phases of ASIC and FPGA designs.

Knowledge of Hardware acceleration/Emulation and prototyping.

Knowledge of Requirements Tracing and High Level Synthesis.

Hands on experience of Riviera-PRO, Active-HDL, ALINT, Spec-Tracer, Cyber WorkBench, Matlab, Simulink, ModelSim, Questasim, Intel Quartus II, Qsys, Xilinx ISE, Vivado, Synplify Pro.

Good understanding of computer architecture and digital logic design

Scripting languages: Python, Perl, shell and Tcl.

Familiarity with revision control concepts and tools (Clearcase, SVN)

Proficient in MS office tools.

Working experience of Linux based operating systems. EDUCATION

Master of Science in Computer Engineering Dec 2010 Villanova University, Villanova, PA GPA: 3.97/4

Bachelor of Technology in Electronics and Communication May 2008 Vellore Institute of Technology University, Vellore, TN INDIA GPA: 8/10 RELATED COURSEWORK

Field Programmable Devices

Hardware Design and Modeling

Embedded Systems Architecture

Hardware DSP

Wireless Communications

Microprocessor testing (M68000)

PROJECTS

Managing the Aldec Cloud Project for scalable simulation resources for peak usage verification needs. Helped deploying the tool on the cloud and finalizing the design flow.

Verifying an ALU operator’s digital logic design using a VHDL testbench and modelsim. Tests are created to perform all required operations an ALU must perform.

Verifying the OFDM processor’s FFT engine design in Verilog using Verilog testbenches. Collecting code coverage data to make sure design is 100% covered. Compare hardware generated FFT results with Matlab model results.

Testing and debugging of various components of a 2G/3G, LTE Software Defined Radio using VHDL testbenches.

Verifying a shared memory access design and debugging for possible bugs using VHDL testbench and modelsim for logic simulations.

Testing the functionality of all the operations of a MC68000 microprocessor under all addressing modes using a VHDL testbench.

Designing a 65C02 Microprocessor using VHDL and writing a test bench to verify an instruction in all addressing modes, performing logic synthesis and timing analysis as a part of Hardware System Design Course.

PUBLICATIONS

Automatic C-to-VHDL testbench generation shortens FPGA development time – EE Times

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