Manikanta Bhagavatula

**** **** *** ******* **., San Jose, CA – 95116 ac6mv5@r.postjobfree.com 704-***-**** GitHub

EDUCATION:

Master of Science, Electrical Engineering The University of North Carolina at Charlotte May 2018

Bachelor of Engineering, Electronics & Communication Engineering Osmania University May 2016

TECHNICAL SKILLS:

Programming Languages: C, C++, Assembly, Python/Java (familiar).

Operating System & CPU Architecture: Linux, 8086, x86/x86-64, ARM, RISCV (familiar).

Platforms: 80386, QEMU, Renesas RX63N, TI MSP 430, Raspberry Pi, ARM7-LPC2148, 8051.

Tools & IDE: Git Version Control, QT(familiar), GNU Debugger, Make Utility, DVM, Oscilloscopes, Logic analyzers, Eclipse, High Performance Embedded Workshop, Code Composer Studio, Keil, Network Simulator-3.

EXPERIENCE:

Electronic Corporation of India Limited – Embedded System Engineer : Jan 2016 – May 2016

Designed & implemented the accelerometer-based accident detection system for vehicles using ARM7LPC 2148 micro controller.

Configured and interfaced the MEMS sensor to the microcontroller which continuously senses the motion of the vehicle.

Worked as a team lead and responsible for the setting up GPS and GSM modules; on an accident, records the location and sends this information to the pre-saved emergency contacts.

Tested the application in real world using bicycles and adopted Agile – Scrum Methodologies.

PROJECTS:

JOS Operating System GitHub C

Implementation of the JOS Exo-kernel for x86 architecture emulated by QEMU.

Memory Management Infrastructure - Designed a physical page allocator, configured page directory and page tables for both kernel and user processes to provide address space abstraction.

Interrupt and Exception Handling - Configured the Interrupt Descriptor Table (IDT), wrote handlers for interrupts & exceptions and implemented protected control transfer from user to kernel mode for execution of system calls.

Symmetric Multiprocessing - Initialized application processors from bootstrap processor using MP configuration table and APIC units. Implemented big kernel lock to provide concurrency control.

Process Management – ‘Implemented a copy-on-write fork to spawn processes, configured pre-emptive round-robin scheduling using timer interrupts and wrote kernel level APIs for Inter-Process Communication (IPC).

Network Driver – Implemented the device driver for Intel 82540EM (E1000) network interface card to help the kernel access the Ethernet. Usage of open-source IwIP as protocol stack and BSD socket interface to communicate with the server. Implemented the system calls to help user programs to access the network resources.

Real Time Priority based Pre-Threaded Image Processing Server GitHub C/C++

Developed an echo image processing server capable of interacting with client threads through a pool of worker threads using the Producer-Consumer model which serves both static and dynamic client requests.

The server consists of main thread and a set of worker threads with main thread running at higher priority.

Used POSIX threads library to achieve preemptive multi-thread execution and semaphores for synchronization.

The server processes the image by applying image processing operations obtained from open source OpenCV Library.

Deployed the project on Amazon Web Services (AWS) to demonstrate the real time functionality of multi-threaded execution of client requests by the server.

Embedded Linux GitHub C

Bare metal programming on ARM using GNU Linker Scripts with QEMU.

Implemented a Linux kernel module, built a kernel image for ARM versatile pb board.

Booted kernel with U-Boot bootloader and implemented the root file system with Busybox to run user programs.

Developed a polling-based UART Device Driver on the emulated QEMU Versatile PB Board.

Cache Simulator and Branch Predictor Simulator GitHub - Cache Simulator GitHub - Branch Predictor Python

Developed a custom cache simulator to simulate the performance evaluation of trace-based input.

Code simulators for one-level, two-level local, two-level global & two-level gshare branch predictors to evaluate the performance of trace-based input.

Performance Evaluation of In-Order Vs Out-Of-Order RISC-V Cores GitHub Scala

Simulated the rocket-chip and BOOM (Berkley Out-of-Order Machine) cores of Berkley’s RISC-V based SOC generator.

Analyzed the behavior of both the cores against multiple benchmark suites.

Modified the architecture of the open-source SOC, analyzed the results of multiple benchmarks for various cache associativity.

Two-way communication between PC using UART and RX63N CAN bus module C/C++

Implemented two-way communication between two computers, capable of transmitting and receiving a stream of characters.

Responsible for setting up transmitter and receiver mailboxes and the communication between two RX63N boards is achieved through CAN bus module.

Established a Queue to store the data from the CAN bus and UART module was used for transferring the data from RX63N to PC.

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