Engineer Electrical Engineering

Prabakar Marikani,

**** ********* ****, ***** ***** 916-***-**** Email: ***************@****.***

OBJECTIVE:

To obtain an entry level position in the field of Analog/Digital Design Verification/Validation. EDUCATION:

Master of Science in Electrical Engineering, California State University, Sacramento, Present. GPA: 3.97 /4.0 Bachelor of Engineering in Electronics and Communication Engineering, CIT, India, May 2012. GPA: 3.6/4.0 TECHNICAL SKILLS:

Programming Language - C, Java, SQL, UNIX, Matlab. Hardware Language - Verilog, System Verilog, VHDL. Scripting Language - PYTHON, TCL, PERL, R, JMP.

Design Tools - Eclipse, Design Compiler, Synopsis VCS, Primetime, Spartan3E, Cadence, PSpice. COMPUTER ARCHITECTURE CONCEPTS:

Parallelism, Multithreading, Cache Coherency, UMA-NUMA, Cache Snooping, Branch Prediction, Pipelining. WORK EXPERIENCE:

Integration & Yield Engineer GLOBALFOUNDRIES, Malta March 2018 – Present

Currently working on route creation, Control parameter verification and SORT parameter analysis for the new product integration Setup.

Involved in Inline parameter collection to verify the correlation between Inline and Electrical parameters for every NPI process flow step.

Performing comparison analysis between the normal Process of Record wafers and Engineering test wafers to improve the production wafer electrical parameters and Yield. Software Engineer TATA CONSULTANCY SERVICESW, June 2012–August 2015

Developed a web based Archival and Retrieval application for a health care client using agile methodology.

Automated the monitoring process by developing a tool which checked the functionality of entire web application and reduced the manual work required for failure deduction and debugging.

Awarded with “Performance Recognition Award” by Client Delivery manager for the automation of monitoring process.

Also performed pre-validation and post-validation tasks to meet client requirements and to resolve any implementation issue in the web application.

Internship Experience:

Product Integration Intern GLOBALFOUNDRIES, Malta May 2017 – August 2017

Performed a research work on improving wafer edge yield by correlating transistor final Electrical Test parameters against wafer Fabrication technology test parameters for large volume of different 14nm Semiconductor products.

Developed automated scripts using Python to collect data for Die level Electrical Test parameters and reticle level FEOL, BEOL and MOL technology parameters data based on different conditions.

Worked on reducing manufacturing contamination defects by controlling fabrication technology Parameters. ACADEMIC PROJECTS:

Design, validation and synthesis of a parameterized first-in first-out (FIFO) buffer

Designed a synthesizable parameterized FIFO using Synopsis VCS tool to meet the timing requirements.

Analyzed and optimized the critical path in the design to improve hold and setup time of the FIFO design.

Used Synopsys 90nm technology library to synthesize the RTL code and designed automated testbench to validate the design.

Design compiler was used to validate timing, area and power requirements and also generated code coverage reports to analyze Verilog testbench.

Timing analysis using Design Compiler:

Designed a 4-bit ripple carry adder, BCD Up/Down counter, Memory and ALU circuit(Using Divide by 9 clock) in Verilog and used PERL to generate inputs automatically and to check the expected result with the actual result.

Identified four timing path requirements in each circuit and synthesized the design using design compiler. Design of a Cache Simulator using PYTHON:

Designed a 4-way set associative cache simulator with MESI Protocol (Bus Snooping) and non-cacheable memory pages.

Using Python OOPS and Files concept implemented LRU scheme for cache memory Read and Write logic.

By implementing random logic, generated read and write requests and observed number of cache hit, cache miss and the cache miss rate at the output.

Design and Layout of a Synchronous Saturating 8-bit Accumulator:

Layout for basic gates like NAND, XOR, Inverters and NOR were designed initially and these layouts were used to design the 8-bit accumulator.

Data and Set/Reset Flip Flop layouts were designed and added to the 8-bit accumulator to implement the Register module for data storage.

Overflow and Underflow logic were added to the design to determine the next cycle input for Accumulator. Achieved equal rise and fall time by adjusting the W/L ratios of NMOS and PMOS appropriately.

Used Cadence Virtuoso for simulation and layout and generated DRC and LVS report.

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