Mr M karthick
seeneerkuppam,
Karayanchavadi,CH-600056.
E-mail-id: ************@*****.***
phone:+919*********,+919********* .
CAREER OBJECTIVE :
I aspire for a challenging position in a professional Organization where I can enhance my skills and strengthen them in conjunction with Organizations’ goals. A self motivated achiever with an ability to plan and execute.
STRENGTH:
Good analytical and decision making ability. Dedicated to Professional and highly motivated towards target achievements.Having the ability to complete the given task. Positive attitude, Friendliness and Flexibility and achieve in success in job.
ACADEMIC PROFILE :
BACHELOR OF ENGINEERING –Electrical and electronics engineering
from St.joseph college of engineering,ch-105-passing year-2015 with 64%.
Higher secondary – from Nav bharath vidyalaya matriculation higher secondary school with 60% aggregate in March 2011.
SSLC – from Nav bharath vidyalaya matriculation higher secondary school with 70% aggregate in april 2009.
ACADEMIC CREDENTIALS:
Industrial visit:
Thermal Power Plant At Ennore.
All India Radio.
BSNL.
AREAS OF INTEREST:
Transmission and distribution
Power system
SOFTWARE/COMPUTER PROFICIENCY:
Hardware and Networking : CCNA – routing,switching,VLAN
Basic knowledge in MATLAB
Basic knowledge in C,C++
Operating system : Windows XP, Windows 7, Windows 8
Application Package : MS office 2010
WORKSHOP ATTENDED :
Attended a National level workshop on “Electrical Circuit Designing Using MATLAB ”on 10th December 2014 at St. Joseph College of Engineering, Chennai.
RESPONSIBILITIES HELD :
Actively worked as a Technical Committee Member in ELVARZ-13
A National Level Technical Symposium Organized by Department of Electrical and Electronics Engineering held at St. Joseph College of Engineering, Chennai.
EXPERIENCE :
* Arunai electricals - banglore, working in contract for 2years.
AWARDS/ACHIEVEMENTS:
Has won several prizes in cricket,chess and carom under school levels
Has served as the Guide in Scout/Guides in school.
ACADEMIC PROJECTS:
TITLE : FPGA for inter-leaved Full bridge converter & Wide Input range
ENVIRONMENT : Open loop(MAT Lab),Closed loop(VLSI programming)
Duration : 3 months
LOCATION : Vee Eee Technologies,Chennai
PERSONAL DETAILS:
Name : Karthick.M
Date of Birth : 13/12/1993
Father’s Name : Manoharan.G
Nationality : Indian
Hobbies : playing cricket,music and chess
Languages Known : proficient in Tamil & English
DECLARATION :
I hereby affirm that the particulars furnished above are true to the best of my knowledge.
Date : YOURS TRULY
Place : chennai
(KARTHICK.M)