Design Project

N KUMAR REDDY

E-MAIL: **.*******@*****.***

PHONE NUMBER: 964*******

SUMMARY:

VLSI Physical Design Trainee at ChipEdge Technologies Pvt Ltd from April 2018 .

Post Graduate holder looking for a career in VLSI Domain.

One academic year experience in teaching.

Strong in basics of CMOS Logic Gate, Digital Circuits and VLSI Physical Design Concepts.

Good academic background

PERSONAL INFORMATION:

Name : N Kumar Reddy

Father’s name : N Adhinarayana Reddy

DOB : 23-12-1992

Gender : Male

Address : Patthepuram Village, Chittoor District, Andhra Pradesh. EDUCATION:

Qualification School/College University Year Degree, Percentage

/Board Specialization /CGPA

M.Tech, Mobile Communication

Post Graduation NIT Arunachal Pradesh NIT Arunachal Pradesh 2017 and Computing 8.9 B.Tech, Electronics&

Under NBKRIST,Nellore VikramaSimhapuri 2014 Communication Engineering 84 Graduation

Class 12 Sri Chaitanya Jr College BIE, Andhra Pradesh 2010 Maths, Physics, Chemistry 94.1 English, Telugu, Hindi, Maths,

Class 10

Chaitanya E.M High

School BSE, Andhra Pradesh 2008 Science, Social 85.3 EXPERIENCE:

Teaching assistance during M.Tech program in Mobile Communication and Computing at NIT Arunachal Pradesh.

SOFT SKILLS:

1. Communication skills

2. Research skills

3. Willingness to learn

4. Self confident

5. Self Motivated

TOOLS:

1. Synopsys IC Compiler, Prime Time, Star-RC.

2. ANSYS HFSS, MATLAB, CST MWS

TECHNICAL SKILLS:

1. CMOS Fundamentals, VLSI Physical Design

2. Digital electronics

3. Antenna Design

WORKSHOPS:

Participated in one Day Internship Programme on “VLSI Physical Design” organized by QSoCs Technologies, Banglore on 31st March 2018.

Participated in the faculty development programme on “Fundamentals of Analog Integrated Circuit Design” organized by E&ICT Academy IIT Guwahati held on 23-31 January, 2017 at Gauhati University.

Participated in the national workshop on “Entrepreneurship: An innovative way for creation of income & employment opportunities” organized by department of management & humanities & entrepreneurship development cell, NIT Arunachal Pradesh from 1st to 7th March, 2016. ACHIEVEMENTS:

Presented a paper on “A novel CPW-fed palm hand type antenna for UWB applications”, IEEE International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET) 2017, Chennai, India.

Achieved First position in the TECHNICAL QUIZ conducted by EXEMPLERS ASSOCIATION.

Qualified in GATE 2014 and GATE 2015 .

PUBLICATIONS:

Conference(s):

N. K. Reddy and R. Jana, "A novel CPW-fed palm hand type antenna for UWB applications," 2017 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), Chennai, 2017, pp. 1568- 1571.

Journal(s):

N Kumar Reddy, Asish Hazra, Vinod Sukhadeve. A Compact Elliptical Microstrip Patch Antenna for Future 5G Mobile Wireless Communication. Transactions on Engineering & Applied Sciences, 2017, 1 (1), pp.1-4. PROJECT: M.Tech

TITLE

Design of RF- Energy Harvesting System to Energize Low Power Electronic Devices. OBJECTIVES:

Design of Multi-Band Antenna to Capture Multiple RF signals from the Environment.

Matching Simulation results of proposed design and Measured results of Fabricated Antenna.

Measuring the Power Harvested from the system.

Project Experience:

Project 1

Technology / Layers : 28nm / 9 Metal Layers.

Gate count : ~300K+

Macros : 16

STD Cells : 71549

No. of Clocks : 4

Frequency : 500 MHz

Tools Used : IC-Compiler, Star-RC, Prime Time.

Role : Design-Import, Sanity checks, Floor Plan, Power Plan, Placement, Timing Optimization, CTS, Routing, Timing Analysis &Closure, LVS& DRC, Design-Closure.

Project 2

Technology / Layers : 28nm / 9 Metal Layers.

Gate count : ~200K+

Macros : 24

STD Cells : 38415

No. of Clocks : 5

Frequency : 350 MHz

Tools Used : IC-Compiler, Star-RC, Prime Time.

Role : Design-Import, Sanity checks, Floor Plan, Power Plan, Placement, Timing Optimization, CTS, Routing, Timing Analysis &Closure, LVS& DRC, Design-Closure.

Project 3

Technology / Layers : 28nm / 9 Metal Layers.

Gate count : 50K

Macros : 6

STD Cells : 10K

No. of Clocks : 3

Frequency : 420 MHz

Tools Used : IC-Compiler, Star-RC, Prime Time.

Role : Design-Import, Sanity checks, Floor Plan, Power Plan, Placement, Timing Optimization, CTS, Routing, Timing Analysis &Closure, LVS& DRC, Design-Closure.

Project 4

Technology / Layers : 28nm / 9 Metal Layers.

Gate count : 450K

Macros : 4

STD Cells : 10K

No. of Clocks : 4

Frequency : 650 MHz

Tools Used : IC-Compiler, Star-RC,Prime Time.

Role : Design-Import, Sanity checks, Floor Plan, Power Plan, Placement, Timing Optimization, CTS, Routing, Timing Analysis &Closure, LVS& DRC, Design-Closure.

HOBBIES:

1. Playing Cricket

2. Listening to music

DECLARATION:

"I hereby declare that the above mentioned information is true to the best of my knowledge and belief". Place: Bengaluru,

Date: 23/07/2018.

(N Kumar Reddy)

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