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Engineer Developer

Location:
Hyderabad, Telangana, India
Posted:
October 01, 2018

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Resume:

KOTTUR VISHAL KUMAR

Mobile: +91-903******* Email: ac68m3@r.postjobfree.com

Career Objective To lead a challenging career in an Esteemed Organization which an opportunity provides for me to learn and where I can contribute my technical skills as professional for the growth of the organization.

Experience Summary 2+ years experience in VLSI namely in RTL Design, synthesis and simulation for Low Area based projects. Good knowledge in VHDL/Verilog.

2+ years experience in GIS and CAD fields namely in Redrafting, Migration and GIS model projects for major telecommunications and broadband services. Good knowledge in Drafting, Migration and Production projects as well.

Work Experience Number of Months : 2 years 1 month Location : Hyderabad / Secunderabad Name of Concern : Trylogic Soft Solutions AP Private Limited Position : Associate VLSI Engineer (RTL Design) Period : November 24, 2015 to December 4, 2017

Number of Years : 2 years 2 months Location : Hyderabad Name of Concern : Apex Knowledge & Technology Private Limited Position : Jr. CAD/GIS Engineer Period : September 12, 2013 to October 14, 2015

Projects – TSS AP PVT LTD Project I Title : Area-Efficient Adder-Based Sign Detector for RNS {2n 1, 2n, 2n + 1} Tools used : Xilinx 14.5 ISE Role : Code developer (Verilog) Description : The moduli set {2n 1, 2n, 2n + 1} has been widely used in residue number system (RNS)-based computations. Its sign extraction problem, albeit fundamentally important in magnitude comparison and other difficult algorithms in RNS, has received considerably less attention than its scaling and reverse conversion problems. This brief presents a new algorithm for the design of a fast adder-based sign detector. Applications : ALU, Communication Systems.

Project II Title : Efficient Design for Convolutive Blind Source Separation Tools used : Xilinx 14.5 ISE Role : Code developer (Verilog) Description : This brief presents an efficient very-large-scale integration architecture design for convolutive blind source separation (CBSS). The CBSS separation network derived from the information maximization (Infomax) approach is adopted. The proposed CBSS chip design consists mainly of Infomax filtering modules and scaling factor computation modules. In an Infomax filtering module, input samples are filtered by an Infomax filter with the weights updated by Infomax-driven stochastic learning rules. As for the scaling factor computation module, all operations including logistic sigmoid are integrated and implemented by the circuit design based on a piecewise-linear approximation scheme. Applications : Digital Signal Processing, Communication Systems.

Project III Title : Design of FPGA CLB Using Asynchronous Semi-Static NCL Circuits Tools used : Xilinx 14.5 ISE Role : Code developer (Verilog) Description : This paper proposes the design of a FPGA Configurable Logic Block (CLB) using Asynchronous Semi-Static NULL Convention Logic (NCL) Library. The proposed design uses three semi-static LUT’s for implementing NCL logic functions. Each LUT can be configured to function as any one of the 27 fundamental NCL Semi-Static gates. The proposed CLB supports 10 inputs and three different outputs, each with resettable and inverting variations. Applications : RF transceivers, small sized batteries.

Project IV Title : Design of Synchronous Gray Code Counter using RL Gates Tools used : Xilinx 14.5 ISE Role : Code developer (Verilog) Description : A Gray Code is an encoding of integers as sequences of bits with the property that the representations of adjacent integers differ in exactly one binary position. There are different types of gray codes: Binary reflected, Maximum Gap, Balanced, Antipodal and Non Composite to name a few. On the other hand Reversible logic has received great attention due to their ability to reduce the power dissipation--an important aspect of low power circuit design. Counters have a primary function of producing a specified output sequence and are thus sometimes referred to as pattern generators.

Applications : ALU, cryptography.

Responsibilities :

RTL Design of each sub modules and top module.

Synthesis and Simulation of modules.

RTL development, resolving system level challenges, architecting, implementing, documenting using Verilog and VHDL concepts

Logical verification of complex RTL designs

Validating them on the boards (FPGA Xilinx).

Good waveform debug skills using front end industry standard design tools like Xilinx ISE and Modelsim.

Projects – AKT PVT LTD Project I Title : GIS Model for Cable TV and Packet Data Client : Comcast Tools used : SpatialNET, AutoCAD, SPATIALweb, RF (Promotion) Tool Role : Production & QC Description : This project involves Redrafting and Migration of Support, RF and Land base Networks. Support Network consists of support structures and segments. RF Network consists of Node, Active Devices, Passive Devices and Cables. Drafting of these networks are done as per source. Finally, the target is Clean up of all these networks with performance of various tools of Comcast.

Project II Title : GIS Model for Verizon Telecom Network Client : Verizon Tools used : IDDS, Microstation Role : Production & QC Description : This project involves drafting of Cable, Conduit, Device, Aerial and Underground Placement with their attributes. Drafting of these Networks are done as per source. Finally, the target is Conversion of Blue prints/Source maps to IDDS Standardized maps of Verizon Telecom Network.

Responsibilities :

The project I scope is to move the following elements to a Comcast-provided landbase within the Spatialnet environment.

Drawing the new and missing Support, RF features and redrawing the data comparing with old data.

Modifying attributes, alignment, addresses as per client source. Support Network-Overhead and Underground (Poles/Pedestals and the corresponding strands/trenches/conduits); RF (Coaxial) Network, comprising the devices and cables and the Fiber Network.

This is a multi-layer project covering the entire Comcast Service territory.

The project II scope is to draft the following elements to a Verizon-provided land base within the IDDS environment.

Drawing the new Cable, Conduit, Device, Aerial and Underground Placement data comparing with old data by giving attributes, alignment as per client source.

This is a multi-layer project covering the entire Verizon service territory.

Software Skills Operating Systems : Windows, Linux Databases : SQL (Oracle, My SQL) Programming Languages : C, VHDL, Verilog Drafting Tools : AutoCAD, Microstation, Bentley Navigator, SpatialNET Hardware Tools : Xilinx, ModelSim, Microwind

Personal Skills

Self-organized and systematic.

Good interpersonal and organizational skills.

Ability to work under pressure and take decisions.

Ready to learn and relearn.

Academic Qualifications

M.Tech in VLSI System Design from Aurora’s Engineering College, Bhongir (Affiliated to JNTU, Hyderabad) with First Class with Distinction 74.88% passed out in December, 2012.

B.Tech in Electronics & Communication Engineering from Aurora’s Scientific, Technological and Research Academy, Hyderabad (Affiliated to JNTU, Hyderabad) with First Class 65.03% passed out in 2010.

Intermediate in M.P.C from Deeksha Junior College, Nirmal (BIE) with First Class with Distinction 88% passed out in 2006.

S.S.C from Sri Saraswathi Shishu Mandir, Nirmal (BSE) with First Class with Distinction 87.33% passed out in 2004.

Achievements

NCC ‘A’ Certificate, Camp Certificate (at Adilabad, 32 Andhra Battalion), won prize in group singing competition and as a volunteer in State Level Volleyball Tournament.

Participated in the adjunct course on HDL for Chip Design at AEC, Bhongir.

Participated in the workshop on Advanced VLSI System Design using SYNOPSYS Tools at AEC, Bhongir.

Certified on Telecom Protocol Development from Convergence Labs, Hyderabad, India.

Academic Projects

B.Tech Academic Project: Title : Efficient FPGA based Distributed Arithmetic Architecture for FIR Filter Role : Code Developer Organization : ASTRA - Vedic School of VLSI Design Description : Traditionally, direct implementation of a K-tap FIR filter requires K-Multiply-and-Accumulate (MAC) blocks, which are expensive to implement in FPGA due to logic complexity. To resolve this issue, there is DA, which is a multiplier-less architecture. It (K=4) includes the shift register unit, LUT and the adder/shifter unit. It gives high speed performance.

M.Tech Academic Project: Title : Distributed Arithmetic Architecture for FIR Filter Role : Code Developer Organization : AEC Description : Traditionally, direct implementation of a K-tap FIR filter requires K - Multiply-and-Accumulate (MAC) blocks, which are expensive to implement in FPGA due to logic complexity. To resolve this issue, there is DA, which is a multiplier-less architecture. It (K=4) includes the shift register unit, LUT, the adder/shifter unit and the parallel adder. DA used to increase the resource usage while parallel structure also used to increase the system speed. In addition, the LUT also used to decrease the required memory units.

Personal Information Father’s Name : K. Vijay Kumar Mother’s Name : K. Pushpa Date of Birth : 15 November, 1988 Languages Known : English, Hindi & Telugu Nationality : Indian Residence Address : H.No: 1-5-90, Sofi Nagar, Nirmal, Dist. Adilabad, Telangana, India – 504106.

Present Address : H.No: 1-5-6/18, C/O G.V. Venugopal, Sri Krishna Colony, Musheerabad, Hyderabad, Telangana, India – 500020.

Declaration I hereby declare that above-mention information is correct to the best of my knowledge and bear the responsibility for the correctness of the above mentioned particulars.

Date: yours faithfully Place: KOTTUR VISHAL KUMAR



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