Design Project

Peter Alexandrov Tentchev

***** ******, *****

E-mail: *********@*****.**

High-level Electronics Engineer with extensive experience in Digital and Analog Hardware, DSP, FPGA, Microprocessors / Microcontrollers and embedded Firmware design.

Skills:

Digital and analog hardware design for telecom - telephone systems, digital data transmission and control systems.

EDA tools – CADENCE, ORCAD, MENTOR GRAPHICS - PADS, ALTIUM DESIGNER. HW Simulation tools – PSPICE, HyperLynx, Modelsim. MATLAB.

Microprocessor/ Microcontroller and DSP Systems - HW and SW real time design: Motorola HC05, HC11, HC16; Intel 8051; Texas Instruments MSP430, DSP DaVinchi Family; Analog Devices ADSP21XX, ADSP21XXX, Motorola DSP 56XXX, Echelon LonWorks Neuron Family, Altera NIOS 32bit Embedded Software Cores, ARM Cortex – EFM32 (Energy Micro; Atmel AVR and MegaRF.

C/C++ real time programming.

Low level programming – Motorola/Freescale, Intel, Analog Device’s assembler languages. FW (programming) design tools – IAR, Keil, Code Warrior, Code Composer.

FPGA, PLD programming - Xilinx Foundation and ISE Tools, Altera QUARTUS, Lattice ISP LEVER Tools.

VHDL – Synopsys, Synplicity, Leonardo Spectrum. Audio Compressing Protocols - G711, G722, G728, H221, MPEG. PCI, PCIe, SATA, CompactPCI, ComExpress, PC104-plus. SOLIDWORKS. CENELEC – EN50155. ISO 9001. RFID.

Work Experience:

November 2015 - present

Colway Industrial S.A., Madrid – www.colway-08.com Project: Hardware electronic design of P.A.S (Public Address System) - railway application. Role: Schematic and PCB design using CADENCE – OrCAD and Mentor Graphics PADS. Project: Hardware electronic design of large Led Dot Matrix Display for onboard railway applications. Role: Schematic and PCB design using CADENCE – OrCAD and Mentor Graphics PADS.

May 2012 – November 2015

March 2014–August 2014

February -May 2014

November 2013- March 2014

January-November 2013

May–December 2012

Contract roles at five companies:

1.Fundación Santa María La Real-Centro de Estudios, Aguilar de Campoo, Palencia Project: C++ Firmware design of Wireless Sensor Network (ZigBee-PRO) based on Atmel MegaRF Microcontrooler. Role: Entire design performance.

2.Phercab, S.L., Madrid (www.phercab.com) Project: Two I/O extension modules (one digital and the other analogue) HW design for the company’s special purposes PLC. Role: Schematics and PCB design using Altium Designer, output to BOM and Gerber files, writing documentation – manuals and datasheets.

3. Marine Instruments, S.A., Vigo, Pontevedra (www.marineinstruments.es) Project: Hardware and firmware design of Bootloader Module with IRDA communication. Role: Schematics and PCB design with OrCad y Mentor Graphics PADS, C/C++ firmware design over ARM Cortex M4 and in Verilog for Lattice FPGA.

4. Sgenia Soluciones, S.A (www.sgenia.com) Project: Modular Control System for Hydrogen Fuel Cell based on Freescale PowerPc microcontroller. Role: Circuits and PCB design. Firmware design in C.

5. Albentia Systems, S.A (www.albentia.com)

Project: Baseband Subsystem of WiMAX Access Point based on Xilinx FPGA

and Freescale QorIQ Processor. Role: Circuits and PCB design using OrCAD amd Mentor Graphics PADS.

Oct. 2006 – May 2012

INFOGLOBAL, S.A., Pozuelo de Alarcon, Madrid,Spain – www.infoglobal.es

Pproject’s Leader in HW/FW Design. Project: Analogue video matrix (crosspoint) 16x16ch module. Expandable up to 128x16ch. Role: Circuits and PCB design. Firmware design in C.

Project: Ethernet switches & controller. Four modules.

Role: Circuits and PCB design. Firmware design in C.

Project: Decryption system for A51(GSM) encrypted communications. Role: VHDL programming on Virtex-5 FPGA platform, using Xilinx ISE tools. Project: CompactPCI modules with ComExpress. Role: Circuits and PCB design.

Sept. 2001 – Oct. 2006

JORNEL, S.L.U., Las Rozas, Madrid,Spain

Project’s Leader in HW/FW Design. Project: Weight measurement unit based on Altera NIOS Embedded IP Processor with Ethernet (TCP/IP)connection. Role: Circuits and PCB design. FPGA programming, using ALTERA QUARTUSII. Firmware design in C/C++ and assembler.

Project: Telemetric and control system via RF UHF-860MHz channel.

Role: Circuits and PCB design. Firmware design in VHDL for ALTERA CPLD and assembler for TI microcontroller.

Project: PCI modules (4 plug-in PC and 2 extensions) for industrial measurement and control.

Role: Circuits and PCB design. ALTERA and XILINX CPLD and FPGA programming, using ALTERA QUARTUSII, LEONARDO Spectrum and XILINX ISE Tools (VHDL and ABEL languages). Design of the test software in C.

Project: Industrial Control Units based on Echelon LonWorks Neuron Network Processor Cores.

Role: Circuits and PCB design. CPLD programming, using ALTERA QUARTUSII. Test firmware design.

October 1998 –September 2001

A E Q, S.A., Madrid,Spain - ISO 9001 Certified Company http://www.aeq.eu/ Sr. Hardware/DSP Engineer. R&D Dept.

Project: Digital audio mixing and distributing matrix with 12x12 AES3 I/O stereo(24x24 mono). 60x60 AES3 (120x120 mono) mixing and distributing matrix can be configured connecting 5 units via high speed parallel LVDS data bus – http://www.aeq.eu/products/impact . Role: Responsible of project’s hardware and firmware design. Personally designed: - software DSP IP core with eight 28 bit accumulators implemented in XILINX FPGA, using VHDL (SYNOPSYS) - circuits and PCB design - host microcontroller firmware. Project: 60 Audio Channel Multiplexed System via E1/T1 network using G722 and ADPCM single and multiband audio compressing with modified predictive algorithm - http://www.aeq.eu/products/ranger Role: Participated in circuits design and wrote the DSP program. Designed two new algorithms: - single band ADPCM audio compressing algorithm at 32 kbps with 13 zeros predictive routine. Algorithms with up to 150 zeros were developed with more than 20dB S/N ratio improvement in respect with G722. - four subband ADPCM audio compressing algorithm at 128 kbps using 6:4:4:2 formula. * This equipment was used at the Olympic Games Sydney 2000 for providing voice and data commentary services.

December 1991 - October 1998

Grupo JPG, S.A., Madrid, Spain, ISO 9001 Certified Company – http://www.grupojpg.com/

Sr. Automation Design Engineer. Responsible of Electronics Automation Subsystems design and manufacturing.

Project: Fuel consumption measurement system based on embedded SIEMENS microcontroller. Role: Responsible of electrical subsystem design – circuits, PCB, firmware programming etc. Project: Hydraulic dynamometer control subsystem with 3 PID cascade loop based on Analog Devices 16 bit DSP and Siemens 8051 microcontroller. Role: Responsible of electrical subsystem design – circuits, PCB, DSP algorithms, firmware programming etc. Project: Testing bench for hydraulic circuits of Airbus 320 Role: Responsible of electrical subsystem design – acquisition circuits, control unit design with Altera CPLDs. Project: Testing bench for 700 kW diesel engine of Leopard tank. Made for Santa Barbara Blindados, Sevilla, Spain – Military Tanks manufacturer recently acquired by General Dynamics. Role: Responsible of electrical subsystem design – acquisition circuits, control unit for hydraulic dynamometer etc. Other projects: Control, test and acquisition systems installed in various military bases in Spain, Universities and companies in Europe and South America.

Role: Responsible of electrical subsystem design.

1989 - 1991

Polytechnic University of Plovdiv, Bulgaria.

Assistant Professor, Dept. of Automation in Electronic Design.

Activity: R&D of Digital Data transmission systems via RF channel. Project: Telemetric control system for urban lighting. Role: Design of FSK modem with non coherent demodulator and code repetition.

1985 - 1989

Polytechnic University of Sofia, Bulgaria.

Research Associate, Laboratory of Automation of Textile Industry.

Activity: R&D of Control systems based on analog and digital PID controllers. Projects: Design of analogue and digital PID controllers and microprocessor based automatic textile dyeing systems. Role: Analogue and digital circuits’ design. PCB design.

Education:

Polytechnic University of Sofia, Bulgaria.

MSEE equivalent degree, graduated in 1985.

Relative Coursework:

C, C++ Real Time Programming.

Digital Signal Processing (Analog Devices ADSP21XX, SHARC 21XXX).

EDA tools - Orcad.

Digital Data Communication via RF channel. Modulation/Demodulation, Encoding/Decoding.

Nationality:

Bulgarian, permanent resident in Madrid, Spain since 1991.

Additional Skills and Interests:

HTML, JAVA.

Graphic Design tools - Corel Draw, Photoshop.

Artificial Intelligence.

Latest Projects

8 and 20 ports Gigabit Ethernet Switches

8 ports Gigabit Ethernet Switch for onboard communication systems. Installed in trains of Mexico DC and Sao Paulo Undergrounds.

18FE + 2GB ports Ethernet Switch for onboard communication systems. Installed in trains of Mexico DC and Sao Paulo Undergrounds.

PC104 four channel MPEG4 Encoder Module

Four channel MPEG4 Encoder Module, PC104 compatible. TI DSP core DM648 was used.

CompactPCI Modules

16 port GB Ethernet Switch, CompactPCI compatible.

COMExpress Carrier board, CompactPCI compatible.

Contact this candidate