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Principal Hardware Engineer

Union City, CA
September 21, 2018

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Shree Kant 408-***-****

Principal Hardware Engineer

Microprocessor, SRAM, Clock, Physical Design, SOC, Statistical Design, Machine Learning, Business Analytics

Rich and diverse experience in high performance, low power, and high-yield microprocessor designs in cutting edge deep submicron Finfet technologies with passion for statistical design techniques. Effectively used innovation, collaboration, and automation to efficiently deliver complex designs on schedule with great quality.

Great problem solving, documentation and communication skills. Proven track record of meeting aggressive schedules with high quality deliverables for 9 generations of SPARC CMT microprocessors.


Microprocessor SRAM array Register File, CAM design for high performance microprocessors

Clock design expertise for high performance, low power and low skew clocks

Semi-Custom Place and Route design for complex embedded logic in custom SRAMs

Timing margin methodology development with AOCV / POCV

Deep knowledge of CMOS planar and FINFET technologies for 10nm / 7nm designs

Expertise on layout dependent effects (LDE) to improve circuit performance and robustness

Cross domain, multi VDD design expertise for DVFS, SOC designs

Memory Complier based design expertise

Statistical design methodology and automation for memory bitcell analysis, circuit design optimization, sensitivity analysis, self timed race margins, flop hold margin characterization and yield improvement

Foundation in Big data, Predictive Analytics and Machine Learning

TOOLS: HSPICE, XA, Smartspice, Cadence Virtuoso, backend verification Mentor Calibre DRC,LVS, Synopsys StarRC, ICC router, Primetime, Statistical Analysis tool JMP, MATLAB, R, Alteryx, Tableau, perl, python, shell

Professional Experience

ORACLE CORP (previously SUN MICROSYSTEMS INC) 1997-Present

Principal Hardware Engineer

SRAM Array Design

Designed SRAMs for high performance multi-port register files and CAM arrays.

Pioneered methodologies for efficient custom circuit variation aware designs in deep-submicron design for SRAMs and register files and CAMs including feasibility of micro-architecture, timing, margins simulation, layout planning, physical backend and functional verification, design sign-off.

Clock Design

Designed and tuned clock grid for high performance low skew, low power microprocessor, reducing clock power by 30% with minimum penalty (< 0.2ps) on clock skew.

Formulated clock skew budgets for max / min architectural critical path timing closures.

SOC Physical Design

Designed and established low voltage timing margin methodology for wire dominated data paths min time closure.

Established and automated the proven and working spice margin methodology, reducing pessimism in the design margins for low voltage, cross domain SOC design for DVFS applications. CDC and UPF familiarity.

Expertise in Floorplanning, place and route, power grid, STA using Synopsys and Mentor Tools

AOCV / POCV Timing Methodology

Pioneered, established, and automated min timing margin methodology for high performance critical timing paths, replacing a fixed derate margin with input slew, output load, logic depth, position in the logic path, distance from the common node and operating voltage, temperature conditions.

Reduced pessimism, enabling easier and faster timing closure on min time critical top CPU timing paths.

Shree Kant Page Two


Designed compiler based memories and familiar with the memory compiler concept, design approach and applications for fast turnaround of configurable memories.

Designed semi-custom sub-blocks in the complex memory using place and route for the data paths and the control blocks and custom logic in memories reducing turnaround time.

Statistical Design & Analysis

Delivered core expertise on statistical design methods and techniques with monte Carlo analysis, designing and optimizing (DOE) robust circuits to mitigate design variability for SRAMs and microprocessors with high yield to meet challenges for latest technologies.

Trail blazed, pioneered and successfully led formulated and established Statistical design methodologies using statistical design expertise enabling high quality, high yield circuit designs.

Established these methodologies to meet design specifications with low risk, high yield, and high quality to help meet aggressive design schedule by judging the risk assessment, mitigating impact of process variability and removing pessimism to meet design goals.

Pioneered, implemented and automated statistical design methodologies for memory cell design, flop characterization and yield analysis, clock skew analysis, design sensitivity and optimization using DOE, self-timed margins, leaker-keeper design, noise budgets etc. improving performance, quality and robustness of the designs.

Mentored engineers, helping them become more proficient in statistical design techniques.

Process and Technology

Studied process and technology issues for planar and 10nm / 7nm FinFet technology to formulate design guidelines.

Pioneered understanding and usage of Layout Dependent Effects, improving design performance.

Developed physical based statistical models for high performance aggressive designs, enabling better understanding and use of design variation.

Contributed great knowledge of NBTI / PBTI transistor aging and impact on designs and methodologies

Performed analysis and methodology for optimum contact coverage on transistors for optimum performance.

Additional Relevant Experience


Sr. Design Consultant

ST MICROELECTRONICS, New Delhi, India 1994-1996

Memory Design Engineer

DCM MICROELECTRONICS, New Delhi, India 1991-1994

ASIC Design Engineer


- HBX Harvard Business School, CORe, Credential for Readiness in Business Analytics, Economics for Managers,

and Financial Accounting 2017

- Certification from Stanford University - Coursera in Machine Learning. 2017

- Udacity Nanodegree in Advanced Business Analytics. 2017

- Business Analytics Specialization from Wharton Business School – Coursera online 2017

Bachelor of Engineering (BE) in Electronics and Communication Engineering with Honors from the prestigious Delhi College of Engineering (DCE), Delhi, India, now called Delhi Technological Institute (DTU) 1987-1991

Awards and Honors

National Merit award and scholarship from Indian Govt. for academic excellence in high school

14 US patents for SRAMs and register file designs. Some of the topics are listed below for reference:

Register file read design scheme for high performance and low power design

High performance address decoding techniques

Efficient method of data transfer between register files

Method and pipeline for performing multiple swap requests to reduce the latency

Adaptive timed keeper control mechanism to reduce leakage and help writeability

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