Design Engineering

Garudadri Ramya

646-***-**** ***.*******@*****.*** LinkedIn: https://www.linkedin.com/in/garudadri-ramya-a3073461 Houston, TX Summary: 2 years of experience working on RTL Design, PCB layout and fabrication with working knowledge of controllers like PIC, 8085, 8086, 8051, low level protocols like SPI, I2C,RS232/485 and knowledge of microarchitecture, Instruction Set Architecture and memory hierarchy

Areas of Interest: ASIC Design/Verification Embedded Engineering SoC Design/Verification Education: Master of Science Electrical Engineering, University of Houston May 2018, GPA-3.8 Course Work: Adv Digital Design, Adv VLSI Design (RICE University), Adv Hardware Design, Adv Computer Architecture, Microlithography, VLSI Design, Adv VLSI(UH)

Bachelor of Science Electronics and Communication Engineering, RGPV, India June 2012, GPA-3.7 Course Work: Digital Circuit Design, Analog Design, CMOS Engineering, Microprocessors, Microcontrollers Technical Skills:

Programming and Scripting Languages:Verilog, SystemVerilog,UVM, Python, C/C++, Perl, TCL, MATLAB, Oracle SQL, PL/SQL Hardware: Altera DE2-115, Xlinx Zynq Zedboard, Altera Cyclone V SoC, Arduino, Raspberry Pi Tools: Altera Quartus, Modelsim, Simulink, Vivado HLS, SDK, Xilinx System Generator, Cadence Virtuoso Layout suite-ADE XL, Silvaco, LTSpice, QuestaSim

Academic Projects:

Design and Verification of APB Protocol, AXI-OCP interconnect Toolkit: System Verilog, UVM Design and development of a multi-player game Toolkit: FPGA DE2-115 board, Quartus II, ModelSim

Implemented state machines, custom Verilog modules and synthesized timer, random number generator, LFSR, ROM based access controls and generated timing constraints for synchronous and asynchronous based systems using ModelSim

Utilized features of the Quartus Prime II design software including IP Generation, I/O Assignments, Compilation, Timing Analysis, Power Analysis, Design Download and Design Debug.

Linear System Solver (RICE University) Toolkit: SysGen, Xilinx SDK, SoC, C, MATLAB, Simulink, Vivado HLS

Integrated programmable ARM core with CORDIC QRD and matrix-multiplication accelerator

Assessed performance speed up of pure algorithmic version with custom IP accelerator interfaced using AXI4-Lite via UART ASIC Synthesis (RICE University) Toolkit: Synopsis DC, SOC Encounter tools

Imported CORDIC HDL code onto ASIC flow tools by edited TCL scripts for place and route Simulation of Cache Organization and Pipeline Toolkit: Python, Simplescalar, SPEC 2000 Benchmark Suite

Analyzed the effect of cache organization on system performance by modifying cache size, block size and associativity

Evaluated L1 and L2 memory access patterns in sim-out order execution; automated to analyze data using scripting tools 4-bit Synchronous Johnson Counter Toolkit: Cadence Virtuoso, LTSPICE, Linux

Designed a 4-bit synchronous Johnson Counter using positive edge triggered D Flip Flops analyzed efficiency along with circuit design, simulation, layout design and RC extractions. Obstacle Detection Robot Toolkit: Microcontroller 8051, Microprocessor 8086, Keil

An autonomous robot which could detect obstacles in its path and avoid any collision using microcontroller, LEDs, resistors, capacitors, crystal oscillators, reset switch and LDR. Invisible Broken Wire Detector Toolkit: Proteus Design Suite, PCB fabrication

This project focused on detecting a faulty wire without replacing the entire core cable and involved PCB fabrication Work Experience:

Intern, University of Houston July 2018-Present

Implementing verification of communication protocols like RS232 on FPGA through UART peripherals

Working on automating the breaking system of a car using Raspberry Pi, Python, and Ultrasonic Sensor. Detects to an accuracy of 0.02 cm. Rings an alarm and brakes the system if the object is near

Pipeline Modelling of RISC Processor MIPS32, working on testbenches to implement the processor data flow.

Working on SoC design and verification using Embedded C, Linux environment Project Engineer, Wipro Ltd. July 2013- July 2015

Involved in functionality of Oracle Applications R12 modules, Reports, Forms and Siebel CRM module

Developed PL/SQL scripts to improve the performance using Stored Procedures, Functions, Packages and Database Triggers Engineering Intern, Bharat Sanchar Nigam Ltd. May 2010- July 2010

Internship involved working with a small multi-disciplinary team which includes all areas of product lifecycle development such as design, code review, software documentation, data analysis, testing, validation

Service and distribution of broadband connections, back-up management, modulation techniques and sources of power Certification:

E.I.T - August 2018

Contact this candidate