Shashank Sanjay

***** ******* ***, *** *****, CA 92126 ac62nk@r.postjobfree.com

619-***-**** https://www.linkedin.com/in/shashank-sanjay-97b69079

SUMMARY

•Knowledge of Signal & Power Integrity concepts such as losses, S-parameters, crosstalk, PCB design rules, termination schemes, differential and common mode signals, length and spacing mismatch, stripline and micro-stripline environments.

•Hands on experience in Analog Circuit Design, Layout Design, Pre and Post Layout Simulations, Parasitic Extraction, DRC, LVS using PSpice, and Cadence Virtuoso for TSMC 300nm technology.

•Solid command over technologies related to Real time Serial data acquisition from Medical devices with high proficiency in developing applications using Python and designing the necessary hardware setup to aid serial communication using Adafruit Arduino boards.

•Comfortable with usage of lab equipment such as CROs, DMMs and testing kits. Also, skilled at soldering and wiring.

EXPERIENCE

•Data Programmer

SHARP Neonatal Research Institute, San Diego, CA September 2017 – Present

oDeveloping a data acquisition application to simultaneously collect, display and store data in real time from various devices such as Near-Infrared spectroscopes, Pulse Oximeters, Oxygen Analyzers, GE ECG Monitors, and Panda Warmer beds using Python.

oDesigning a pressure sensor circuit using Adafruit Arduino with A/D converters to measure and transmit airway pressure data.

oMaintaining a detailed and well-organized documentation of all test procedures, designs and workaround procedures.

oPreparing a training program and using the same to train the non-technical staff.

•Instructional Aide for Robotics and Computers

SDSU Upward Bound, San Diego, CA June 2017 – July 2017, June 2016 – July 2016

oAssisted students in programming path follower robots using Parallax Boe-Bots.

oGuided students in developing their own apps using MITAppInventor.

•Technical Support Engineer

Hewlett-Packard

Bengaluru, India June 2014 – May 2015

oOpen and track to resolution; vendor, carrier, and internal tickets.

oCreate/maintain documentation of solutions used (workarounds, procedures, etc.).

EDUCATION

•Master of Science in Electrical and Computer Engineering

San Diego State University, San Diego, CA Awarded December 2017

•Bachelor of Science in Electrical and Electronics Engineering

R.V. College of Engineering, Bengaluru, India Awarded May 2014

TECHNICAL SKILLS

•Languages: Verilog, SystemVerilog, Assembly, C, C++, Java, Python, Shell, HTML 5.

•Tools: MATLAB, Simulink, Keil, Ride, Xilinx Vivado, Xilinx ISE, Cadence Virtuoso 6, NCVerilog, Synopsys, Mentor Graphics ICStation, LabView, PSpice, Agilent ADS, Maxwell 2-D, Rogers MWI.

•OS: Windows, Ubuntu, Mac.

PROJECTS

•Design of a 90-Ohm differential line for high speed data transfer across a motherboard

Width and spacing for a loosely coupled differential line and tightly coupled differential line were obtained using the Rogers tool. Minimum width and spacing was maintained at 3 mils. The results were verified with the transmission line simulator Maxwell 2D. The p.u.l. L and C matrices were extracted and the field plots for even/odd mode excitations were plotted. A simulation setup was generated, and the eye diagrams were calculated based on the differential lines designed. Lossless lines with a length of 50 cm and pseudo-random-bit-stream (PRBS) data at 10 Gbps were assumed. A termination scheme for best signal integrity was suggested. Mismatched lengths were created to check for skew while maintaining a 50% eye height.

•Design of CMOS operational transconductance amplifier (OTA) with consideration of performance, chip area and temperature variations

Designed an OTA circuit to attain minimum differential voltage gain of 30 V/V and minimum bandwidth of 30 MHz with operational temperature range: 0ºC to 85ºC, along with the design for the layout using techniques such as common centroid, dummy device, shared source-drain and perform DRC and LVS checks.

•Design of a 2-stage differential-to-single-ended amplifier using TSMC 300nm technology

Designed a 2-stage differential-to-single-ended amplifier with the ability to drive 10pF capacitive load with minimum overall voltage gain of 250 V/V and bandwidth of 30 MHz

•Design of various types of Common Source amplifier with consideration of layout parasitic effect on gain-bandwidth using TSMC 300nm transistors

Designed circuit and layout for passive load, diode-connected load and current source load common-source amplifiers with minimum gain of 15.

•TSMC 300nm modeling IV extraction, long-short channel and temperature effect

Run DC analysis to obtain the drain current-drain voltage curves and drain current-VGS curve of the (W/L=10, using minimal length allowed by the TSMC 300nm technology) NMOS and PMOS in saturation region at 0ºC, 25ºC and 85ºC.

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