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C, C++, JAVA, Android Studio, Embedded C, Verilog using HDL.

Location:
India
Salary:
1
Posted:
September 14, 2018

Contact this candidate

Resume:

B Raj Santhoshi - Resume

Email Id : ac61qy@r.postjobfree.com

ac61qy@r.postjobfree.com

Mobile No: +91-778*******

+91-834*******

+91-944******* (Father)

Career Objective :

I am looking for an opportunity in a reputed organization which will help me deliver my best and improve my skills in engineering and where my resourceful academics skills will add value to organizational operations.

My Area :

IT Product Design and Development and I have working knowledge in C, C++, JAVA, Android Studio and VLSI using Verilog HDL – Xilinx / Z-board, Embedded C / Digital Image Processing using MATLAB. I have also done projects using the above skills. I hope, my skills may match to the product design and development. If given an opportunity, I will work hard for the growth of the organization. Academic:

Qualification

Discipline Institution /

Place

University /

Board

Year of

Passing

Aggregate%

/CGPA

B.Tech

Electronics and

Communication

Engineering

GMR Institute

of Technology,

Rajam.

JNTU Kakinada

2018

First Class

6.57 (CGPA)

Intermediate

M.P.C

Narayana Junior

College

Board of

Intermediate

Education, A.P

2014

First Class

89.7%

SSC

Maths, Science,

Social etc.

Suresh IIT

Concept School

SSC

2012

First Class

9.2 (CGPA)

Technical:

Digital VLSI

Design using

HDL Internship

Digital VLSI

Design using HDL

C-DAC

Hyderabad

C-DAC

(Under Ministry of

MeitY, GoI)

June 2016

Passed

(Certificate

Course)

Technical Skills:

Programming Language : I have working knowledge in : C,C++, Android Studio, JAVA

Tools & Working Knowledge Working knowledge on Verilog using HDL – Xilinx / Z-board, Eclipse IDE, Digital Image Processing using MATLAB. Multisim 14.0, Digital Image Processing / Logic Design, Electromagnetic Waves & Transmission Line.

Work Experience : Working on Purely Temporary (without salary/certificate) in Big IT Company From 7th May 2018 onwards to acquire knowledge in the Projects: Acquired knowledge on the following in the various Projects:

Working on C, C++, C#,

JAVA, XML

Python

Android Studio

Working on Eclipse IDE

Working on Ubuntu 17.04

Using Linaro GNU Compiler

Using APK Analyzer (Android Studio).

Working on VLSI Design using Verilog HDL.

Xilinx – ISE Simulator.

Projects Done :

Done project at C-DAC, Hyderabad on VLSI Design on

“Advanced Encryption & Decryption Standard using Xilinx”. Security is the weighty part in wireless communication system, where more randomization in secret keys increases the security as well as complexity of the cryptography algorithms. The AES is used to protect data in cryptography. It is a symmetric block cipher in which encryption and decryption is takes place. For the performance AES algorithm is discussion from its starting publication. The propose method is to design AES algorithm by using Xilinx ISE 13.1. The simulated result shows the different parameters such as power and time of AES algorithm the hardware implementation of the AES algorithm is created for external data storage unit in application. Rijndael is a symmetric block cipher which can process data blocks of 128 bits (4 words), AES is dived into three types, namely AES- 128, AES -192, and AES -256, In this algorithm 128, 192 and 256 is a key length for the above three types and 10,12 and 14 rounds respectively are takes place. In cryptography, the AES is also known as Rijndael which is a block cipher decide as an encryption standard. It is capable to protect sensitive information. This algorithm is a symmetric block cipher, which encrypt and decrypt information. Encryption converts data in to cipher -text. Decryption of the cipher -text converts into its original form that is plaintext. AES generally allows a 128 bit data length that can be divided into four basic operation blocks. These blocks are Substitute Bytes, Shift rows, Mix columns, Add round key. The algorithm starts with the Add round key stage for both encryption and decryption algorithm. Project done on “A Glove based Gesture Controlled Quad Copter” In this project we present an approach to control a Quad copter by merely using hand gestures. It helps us to propose a way to accomplish Human Computer Interface. The idea is to extract an old techniques of controlling a Quad copter using joysticks, computer controlled etc. with more intuitive technique, that is, by controlling the Quad copter with the help of hand gestures, which will make it more user friendly, as the user would not have to study or learn about different instructions to control different parameters of a Quad copter, because these parameters will be controlled and adjusted with the help of algorithm interfaced to the hand gesture inputs. Here we propound an approach to achieve the illustrated idea by employing image processing technique using webcam. Simple video camera is used for computer vision, which helps in monitoring gesture representation. This approach consists of following modules:-

A real time hand gesture formation monitor and gesture capture

Feature extraction

Pattern matching for gesture recognition

Command determination corresponding to shown gestures and performing action respectively Real time hand tracking technique is used to control the quad copter in real time. If hand gesture is shown in front of camera, the camera captures the gestures. Object of interest is extracted from the background and the portion of hand representing the gesture is cropped out. Extracted hand gestures are matched with the stored data base of hand gestures using pattern matching. Corresponding to the matched hand gesture action is performed by the quad copter.

Project done on “Performance Enhancement of a Hybrid I-bit Full Adder Circuit” Full adder is a crucial requirement for designing many types of processors like microprocessors, digital signal processors, image processing and various VLSI applications etc. In most of the design adder connected on most critical path of the circuit which affects the overall performance of the system. This paper proposes modified hybrid full adder circuit that enhances the performance in terms of power consumption at various voltages, temperature and operating frequency. It also improves noise immunity by 2-5% than its peer design. All simulations have been performed at 45nm process technology on Tanner EDA tool. Full adders, being one of the most fundamental building blocks of all the former circuit applications, still a centre focus domain of the researchers' bygone the years. Among all arithmetic operation the addition is a basic one and acts as the origin of other operations like subtraction, multiplication, division, address generating and so on. The most important feature of modern electronics is low power and energy efficient active block that set up the implementation of all devices that are operated by battery. For different type applications, various types of logic styles are used for designing a full adder cell. For performance analysis of different-2 full adders different parameters are calculates like average power dissipation, delay, number of transistors in used and PDP of circuit. In a design it is interpreter desired that the circuit consumes less power, have very less delay with respect to low supply voltage and avoid noise in output voltage . There are various logic styles having its own merits and demerits, was discovered to implementl-bit full adder cells speed. The design of low delay as well as power VLSI architectures requires adequately ALU (arithmetic processing units), which are used to revise the prime parameter as above stated. Addition is one of the only universal or nucleus operation which is relevant in many task like; subtraction, multiplication, division etc. It is very important to choose the adder topology that would give the way of desired performance.

Term Paper - “High Efficiency Video Coding (H.265 / MPEG-H)” Compression performance of a video codec is very important to enable it to encode high quality videos at low bitrates. Significant progress has been made in the area of video encoding. The latest state of the art video encoding standard, High Efficiency Video Coding -- HEVC/H.265 doubles the video quality for the same bitrate compared to other codecs. This paper presents quality & performance comparison amongst H.265, H.264 and, Motion JPEG using different video encoding libraries. Alongside the need for high compression efficiency, it is also important to keep in the computational complexity of video codecs. In this regards, although HEVC provides the best compression efficiency, it does so at the expense of significantly more computational cost than H.264. The results of the conducted experiments show that HEVC produced best quality video followed by H.264. However Motion JPEG encoding produced fastest encoding times followed by HEVC. Videos encoded with Motion JPEG using OpenJPEG library produced the worst results in terms of quality. H.264 was the slowest among the video codecs and often produced video quality comparable to videos encoded with Kakadu (Motion JPEG). This work is meant to provide insights regarding choice of the video encoding suite & future development of the codecs. Workshop, Seminars & Fest :

Got Certificate for participation in the IC Engine Workshop (19th & 20th Feb 2016) organized by ARK Technosolutions / Robokart in association with IIT Madras.

Got Certificate for participation in the PYTHON Workshop (25th & 26th Feb 2016) organized by Developers Hub suring SAMYAK 2016 at KU University, Guntur.

Got certificate for participation in the Project Design Contest (27th Jan to 29th Jan 2017) on Glove Based Gesture Controlled Quard Copter organized by GMRIT (National Level Student Technical Paper, Project Context & Exhibition).

Got certificate for participation in the ECE Paper Presentation ATMOS 2016 – Techno – Management fest on BITS, Pilani, Hyderabad.

Personality Traits:

I can work under pressure and hardworking

I can handle situations accordingly

I am eager to learn new things

Methodological in nature and self motivational

Participations:

Member in the Technical Fest IGNITION 2K14 held at ANITS, Vishakapatanam.

IEEE and ISTE - Student member.

Participated in Projects exhibition in GMRIT.

Performed Dance on Annual Day Celebrations in 2016 at GMRIT.

Flashmob dance performed at CMR Central, Vizag (College Promotional activity). Interests / Hobbies:

Reading Technical books/magazines.

Dancing – Dance performed in the college events.

Anchoring on the stage / dais.

Personal Profile

Name : B.Raj Santhoshi

Date of Birth : 05/08/1997

Sex : Female

Nationality : Indian

Marital status : Un-married

Languages known : English; Telugu and Hindi.

Passport : Yes I have.

Permanent address : C/o. Shri Kodidasu Venkata Rama Murty Late Door No: 6-61, Rajugari Street, Parvathipuram Town, Vizianagaram- 535 501 (Dist), Andhra Pradesh.

DECLARATION:

I hereby declare that the above written particulars are true to the best of my knowledge and I will be solely responsible for any discrepancy found in them.

I have working knowledge in C, C++, C#, Android Studio, Eclipse IDE, JAVA, VLSI Design using Verilog HDL – Xilinx / Z-board / Embedded C / Digital Image Processing using MATLAB. I have also done projects using the above skills. I hope, my skills may match to the product design and development. If given an opportunity, I will work hard for the growth of the organization. Place:

Date: (Raj Santhoshi B)



Contact this candidate