Resume

Sign in

Electrical Engineering, RF, analog

Location:
Philadelphia, Pennsylvania, United States
Salary:
90K
Posted:
September 11, 2018

Contact this candidate

Resume:

Boya Li

**** ****** ******, ***. ***, Philadelphia, PA 19104 ac60j6@r.postjobfree.com 215-***-****

Education

University of Pennsylvania, Philadelphia, PA May 2018 Master of Science in Engineering, Electrical Engineering. Cumulative GPA: 3.87/4.00 Xi’an Jiaotong – Liverpool University, Suzhou, China July 2016 Bachelor of Science in Engineering, Electrical Engineering. First Class Honors. Rank: 1st of 120 Skills

Tools & Technologies: Cadence Virtuoso, Agilent ADS, Matlab Programming Languages: Python, Java Knowledge: RF Engineering, Analog Circuits, Circuits Design, Electrical Engineering, Layout, Simulation Internships

Engineering Intern, GuradBot Inc, Stamford, CT Jun 2017-Aug 2017

Increased power efficiency 5% by improving power management system

Stabilized robot’s movement through literature reviews, design testing, and parameters tuning

Debugged and flashed main circuit board with motor controllers, GPS, Ethernet and radio mounting

Assembled/Disassembled robot based on mechanical design change and software testing needs

Summarized data in reports including user manual and battery charging guidance Electrical Engineering Intern, STATE GRID Corporation of China, China Jun 2014-Aug 2014

Designed power flow in smart grid to conserve energy by minimizing transmission loss

Analyzed statistics from major installations to evaluate working condition of equipment

Investigated operation principles and techniques on construction of transformers and power grid Selected Projects

RF Receiver Design, Integrated Comm Systems Jan 2017-May 2017

Designed and simulated following subparts using 0.6um process on Cadence Virtuoso Suite:

- A multi-stage common source LNA with 3.28dB noise figure (18% improvement)

- A double balanced active mixer with RF-LO, LO-RF, LO-IF isolations > 40dB

- A cross-coupled LC oscillator with -141dBc/Hz phase noise at 1MHz (28% better than requirement)

- A 474MHz-520MHz dynamic frequency divider with factor of 2

- A 490MHz PLL with bandwidth of 5.2MHz

Implemented Hybrid pi model on inductors using ASITIC to model parasitics and non-idealities

Tested and modified parameters based on simulation performance RFIC Components Design, RFIC Design Jan 2017-May 2017

Designed and simulated LNA, PA, SSA, Oscillator using IBM cmrf7sf technology on ADS

Extracted layout in Cadence into ADS for performance comparison

Appreciated design tradeoffs for power, noise, gain, matching, linearity, and stability Bicycle Energy Harvesting System Jun 2015-May 2016

Conceptualized and constructed integrated circuit on PCB to store energy

- Created and manufactured pedal prototype to generate piezoelectric energy

- Converted output power from rotational generator into useful form

- Designed single harvesting system to integrate two power sources

Built test platform to analyse output power and efficiency of system

Achieved 5% phone charging for 30min ride of bicycle



Contact this candidate