RITU WALIA

Greater Boston Area, MA 531-***-**** www.linkedin.com/in/ritu-walia/ ac5xrh@r.postjobfree.com EDUCATION

Master of Science in Electrical Engineering, GPA: 3.5 University of Massachusetts Lowell Aug 2018 Bachelor of Engineering in Electronics, GPA: 3.5 Priyadarshini College of Engineering, India June 2014 RELEVANT COURSEWORK

• VLSI Design & Fabrication (Clean-room experience)

• Microprocessor & Microcontroller

• Microelectronic Mechanical Systems (MEMS)

• Introduction to Quantum Electronics

• Advance VLSI Design Techniques

• Solid State Electronics

• Biosensors

• Analog Electronic Circuits

• Digital System Design

• Verilog and VHDL

• Logic Design

• Computer Organization

EXPERIENCE

Nagpur Beverages Pvt. Ltd., India: Trainee Engineer Feb 2016 – Nov 2016

• Conducted the troubleshooting during interventions of the bottling lines, including blowing machines, packaging machines, label machines and filling machines and designed the additional modifications on the bottling lines.

• Supervised the market survey.

Nagpur Today, India: Digital Media Manager June 2014 – Nov 2015

• Supervised Social Media Marketing and Analytics, Management, Content Creation & Curation and Reputation Management.

• Planned and conducted business promotion that represented the organization in the market, through online and offline tools. Zero Gravity, Dr. Shrikant Jichkar Foundation (NGO): PR Manager Jan 2011 – Nov 2016

• Designed and planned the website content.

• Supervised conventional and social media marketing of the firm using various SEO tools and MS Office Suite. ACADEMIC PROJECTS

JFET/Dual Gate MESFET with Quantum Well Channel Sept 2017- Present

• Working on obtaining a parallel channel equal to the wavelength of an electron using the variations in the work function. 4-Bit Adder/Subtractor using Cadence EDA tool in 45nm CMOS process and Verilog for designing a DSP-RAM

• Carried the analysis of various Full Adder Circuits in Cadence Virtuoso to find the low power design to be used in DSP-RAM.

• Designed and simulated 4-Bit Ripple Carry Adder/Subtractor using Cadence Virtuoso to generate schematics of basic cells.

• Performed LVS and DRC checks at every stage, and obtained supply voltage v/s power-delay outputs characteristics. 8-Bit ALU using Cadence EDA tool in 600nm CMOS process and Verilog Sept 2017- Dec 2017

• Designed and simulated 8-bit ALU using Cadence Virtuoso to generate layout and schematics of basic cells.

• Verified circuit in Verilog using gate level modelling Mammography Image Processing Sept 2017- Present

• Working on differentiating the cancerous cells from blood vessels with higher accuracy on mammograms using required codes and algorithms with computer processing.

Ergonomic Transducer Design for Endoscopic Optical Coherence Tomography Jan 2017 - Aug 2017

(Paper Published, Electronic Science Technology and Application, 2018)

• Designed a micro-mirror system actuated by electrostatic force with low operational voltage, which has its utility in the fields of optical communications, robotics, medical devices, transportation systems etc. Design of Catheter used in IVUS using silicon micro-mirror Jan 2017 – May 2017

• Worked on obtaining a catheter design using silicon micro-mirror to obtain better accuracy of the penetration angle into atherosclerotic plaque.

SMS based Pet Feeder using Microcontroller ATmega32 Aug 2013- Mar 2014

• Designed a GSM modem based pet feeder using Microcontroller ATmega32. Implemented using Embedded C language. Edge Detection using Sobel Operator Aug 2013 - Mar 2014

• Detected the edges of a grey scale image using Sobel Filter and applied low pass filter to smoothen the edges.

• Project implemented using Linux and C++.

SOFTWARES & LANGUAGES : Cadence (Virtuoso, Spectre), MATLAB, C, Verilog, VHDL, PSpice, Multisim, MS Office Suite CERTIFICATES : Embedded C, Google Analytics, Google Adwords, C++ LEADERSHIP AND ACHIEVEMENTS

• Granted Provost’s Graduate Fellowship at the University of Massachusetts Lowell

• Vice President of Indian Graduate Students’ Association, University of Massachusetts Lowell

• Participant at the International IEEE: 60th IEEE MWSCAS

• National Award Winner for Cultural Dancing at Republic Day Parade, India

• Executive Head of the Cultural Department, Priyadarshini College of Engineering, India

Contact this candidate