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Engineer Design

Rochester, New York, United States
June 13, 2018

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Vedant Karia

Cell: +1-585-***-****, Email:



Seeking Full-Time opportunities where I can implement my ideas to develop and expand my skills in the field of Embedded Systems, VLSI– hardware design, testing and verification.


• Programming Languages: C, C++, Verilog, System Verilog, MATLAB, Perl, C-shell, SQL, Java.

• Software Tools: Cadence Virtuoso, Cadence OrCAD, Multi2Sim, Quartus, Vivado, MATLAB, LabView, Excel Macros, QTP.

• Embedded Processors: STM32 ARM Cortex M0, Beaglebone, Raspberry PI, Arduino, AVR, MSP430.

• Relevant Courses: Design of Computer Systems, Real-Time Embedded Systems, Design and Test of Multi-Core Chips, Advanced Topics in Digital Systems, Design of Digital Systems, Brain Inspired Computing. EDUCATION

Master of Science: Electrical Engineering - GPA: 3.87 May2018

● Rochester Institute of Technology, Rochester, NY Bachelor of Engineering: Electrical and Electronics – GPA: 3.6 May 2014

• Manipal Institute of Technology, Manipal, India. WORK EXPERIENCE

Research Assistant, Rochester Institute of Technology Sep 2017- Dec 2017

Electronics Engineer, Sirena Technologies Pvt Ltd, Bangalore, India June 2015 - July 2016

• Controlling Servo motor at each joint of NINO using the Linux based platform in microchips SOC.

• Sensor integration on the bot, Distance sensor, LEDs, Touch sensor.

• Integrated IMU on the development platform of NINO.

• Smart servo motor design which includes software as well as hardware.

Project Engineer, Wipro Technologies Dec 2014- Jun 2015

● Automation testing and database testing using QTP and selenium web driver PROJECTS

Holographic Reduced Representation on Embedded platform (2018):

• Implementing HRR with convolution memory on Raspberry Pi.

• Encoding and decoding techniques like Circular convolution and Circular correlation are required for reduced representation.

• Improving the training and testing time of HRR by parallelizing the process by adding threads. Processor design (2017):

• RTL design and Verification of 12bit Non-Pipelined RISC processor- Von Neuman Architecture which includes Manipulation, Data Transfer and Flow Control Instructions.

• Designing an Assembler for the Processor and modifying the processor to a 4-stage pipelined architecture which includes cache.

• Designing a multicore processor using the processor designed and testing the design with a 4x4 matrix multiplication benchmark.

Neural Network on Embedded system platform (2017)

• Extreme learning machine implementation on Beaglebone Black Processor.

• Classification of numeric digits captured on the camera. Neural Network Design on FPGA (2018)

• Designing three layered Extreme learning machine on FPGA for classification of images.

• Fixed point precision design with 200 hidden layered neurons. Digital Design & Verification (2016):

● Designing and verification of Basic gates layout 16-bit carry select adder with Boundary scan cell using Cadence Virtuoso.

● RTL design of the arbiter that grants the control of the signal to be processed depending on the requests using a finite state machine.

● Design and verification of ADPCM Codec in Verilog using the cadence.

● Verification of Multi-Core systems and comparing the performances of x86 processors arranged in different Network on Chip topologies using PARSEC benchmarks.

Real time embedded systems:

● Controlled PWM based Servo motor using STM32L476 Discovery board.

● Designed banking system using the QNX system

● Designed ultrasonic sensor based embedded system on QNX software platform.

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