Engineering System

SHAHBAAZ AHAMAD SHAFEEQ AHAMAD

Phone: 352-***-**** E-Mail: *******@***.*** LinkedIn: linkedin.com/in/shahbaazahamad/ 4000, SW 37th Blvd, Apt 512 C, Gainesville, Florida 32608 EDUCATION

University Of Florida, Gainesville GPA:3.833 Aug 2016 – May 2018 Master of Science, Electrical and Computer Engineering Visvesvaraya Technological University, Belagavi, India GPA8.82/10 Aug 2011 – May 2015 Bachelor Of Engineering, Electronics and Communication engineering EXPERIENCE

Research Assistant CHREC Labs, University Of Florida Mar 2017 – Apr 2018

• Developed the FPGA accelerated designs in RTL (Verilog) with profiling and Optimization for improving and achieving highest possible performance.

• Achieved benchmarking of applications with C++ and OpenCl in SDaccel environment for verifying CAPI interface developed to provide productive and scalable framework for coherent FPGA System. Volunteer Researcher Institute Of networked Autonomous systems, UF Nov 2016 – Feb 2017

• Constructed the position calibrating system for autonomous underwater vehicle.

• Installed the embedded system based around the IMU sensor to measure co-ordinates and eliminate all errors generated in arduino environment.

PROJECTS

Reconfigurable Computing 1-D Time Domain Convolution Designed custom circuit to accelerate the convolution, In the process exploited data parallelism, loop unrolling and synchronization across multiple clock domains by bypassing metastability. Project is done in VHDL on Xilinx Environment. Project was implemented to Xilinx 7 series FPGA.

Verification (System Verilog) Verification of Ethernet switch Implemented a Full verification environment for a 2x2 Ethernet Switch, System Verilog constructs such as interface, clocking, assertions, random constraints and functional coverage was used in the testbench. Digital Design 32-bits low power pipelined MIPS processor design Designed custom 32-bits MIPS processor with clock gating to optimize power. Entire 5-staged pipeline was designed with a hazard detection unit using Verilog and performed placement and routing on the generated schematic. Embedded Systems Conversion of manually driven motorcycle To automatically driven Designed Embedded system with the AT89S52 Microcontroller to automatically operate the clutch, brakes and gear. Designed PCB for the circuits incorporating motor drivers, microcontroller. Programmed in VHDL and EMBEDDED C FPGA Design (Hardware Security) Implementation Of Physical Uncloanable Function (PUF) Implemented arbiter PUF and Feed forward Arbiter PUF using structural modeling in vivado environment using VHDL. Computer Architecture Enhancement of Cache hit rate Developed an algorithm based on SCIP (selective cache insertion and bypassing) and LRU (Least recently used) to improve the cache-hit rate by a comparable amount. Used Simplescalar to determine results. Computer System Design Distributed File System

Designed custom FUSE file system including servers and clients incorporating the XMLRPC procedures. Entire design was done in Linux using PYTHON various aspects of fault tolerance like redundancy and checksum were also implemented SKILLS

Languages/frameworks: C, C++, Python, VHDL, Verilog, system Verilog, Opencl Digital RTL Design tools: Xilinx ISE, Xilinx Vivado, Modelsim, Cadence, Quartus, SDaccel Miscellaneous: UVM, Linux, Kernel programming, FUSE file system, Device drivers, MATLAB Certification:

• “SOC Verification using SystemVerilog” In detail course about the various aspects of system Verilog coding applications specifically for Verification. Certification url: https://www.udemy.com/certificate/UC-EJJUUIRA/

• “Learn to build OVM and UVM test benches from scratch” Course teaching verification in detail with the main focus being UVM test benches. Certification url: https://www.udemy.com/certificate/UC-PAXLMN74/

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