MANSI DARJI

**** ******** **, **** **** Beach, FL-33409

ac5gs5@r.postjobfree.com 561-***-****

OBJECTIVE

To seek a position in a dynamic and challenging area of electronics and communication engineering, with an esteemed organization, which will help in my career growth while fulfilling organizational goals.

SKILLS & ABILITIES

Languages:

C, JAVA, VHDL, VeriLog HDL

Software Tools:

MATLAB, Altera Quartus, Xilinx, Eclipse IDE, Proteus ARES,

LabView, Qsys.

Simulation Tools:

ModelSim, ProSPICE

FPGA:

Stratix III, Spartan 3E, CycloneV

Controller:

8051

EXPERIENCE

INTERNSHIP, SPACE APPLICATION CENTRE (SAC), INDIAN SPACE RESEARCH ORGANIZATION (ISRO).

AUGUST 2015 – JULY 2016

EDUCATION

SNPITRC, VIDHYABHARTI, BARDOLI, GUJARAT TECHNOLOGICAL UNIVERSITY, INDIA

- M.E., ELECTRONICS AND COMMUNICATION ENGINEERING

2014-2016

Specialization in Signal Processing and Communication

Achieved First Class with Distinction

BHAGWAN MAHAVIR COLLEGE OF ENGINEERING AND TECH., GUJARAT TECHNOLOGICAL UNIVERSITY, INDIA

- B.E., ELECTRONICS AND COMMUNICATION ENGINEERING

2008-2012

Achieved First Class with Distinction

PROJECTS

1)Design, Simulation and Implementation of Spread Spectrum Modulation for MSS Band using FPGA

-ISRO

A Direct Sequence Spread Spectrum Sequence System is implemented on Stratix III development board with unique Gold Sequence implemented with two 5-bit LFSR’s. A Root Raised Cosine Filter is also designed to reduce the inter Symbol Interference between Signals.

Tools used: Altera Quartus 9.1 Version, Modelsim Altera 13.1, Matlab, Stratix III EP3SL1501152 FPGA, SignalTapII Logic Analyzer, Oscilloscope, Spectrum Analyzer and Vector Signal Analyzer.

HDL Language: VHDL and VeriLog HDL

2)Emulating USB on SoC for Satellite Distance Education System

A Soc device is emulated as a mass storage where the data from DTH is temporarily stored. This stored data is then passed to the PC in form of packets which includes MAC/IP address of the PC at the start of each packet. The software implementation has been done in Xilinx SDK, where the Integration of Ethernet implemented using RTOS with the USB stack has been done.

Tools used: ZedBoard (Cortex A9 processors), Cyclone V SocKit, Qsys, Altera Quartus.

HDL Language: VHDL and C/C++.

3)GSM Based SMS Driven Notice board

-BE Final Year

A set of commands called AT-Commands and HyperTerminal was used for interfacing. It is proposed to design a model where the message to be displayed is sent through a SMS from an authorized transmitter. The toolkit receives the SMS, Validates the user and displays the desired information after necessary code conversion.

Tools used: 8051, HyperTerminal, Proteus

Language: AT commands and Embedded C

4)Automatic Room Light Controller with Visitor Counter

A Controller based model to count number of persons visiting particular room and accordingly light up the room. IR Sensors were used to know present number of persons.

Tools used: 8051, Proteus

Language: 8051 Assembly language

EXTRA CURRICULAR ACTIVITIES

Paper “Design and Simulation of Spread Spectrum Modulation using FPGA” presented and published in EIOCD (Engineering: Issues, Opportunity and Challenges for Development) international conference held at S. N. Patel Institute of Technology and Research Centre, Umrakh on 9th April 2016.

Paper “Review Paper on Image Enhancement Technique” presented and published in EIOCD (Engineering: Issues, Opportunity and Challenges for Development) international conference held at S. N. Patel Institute of Technology and Research Centre, Umrakh on 11th April 2015.

Participated in NIIT National Aptitude Test held in 2009 – Secured 2111rd rank out of 73122 candidates.

Participated in ‘Creative Pool’ held by AEGIS on 2010.

Participated in Paper Presentation in ‘TECHNOCRAT’ held by BMCET.

Won Poster Presentation and Junkyard Wars in ‘RENAISSANCE’ held by BMCET in 2010.

Got 2nd Prize in Junkyard Wars in ‘RENAISSANCE’ held by BMCET in 2011

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