Electrical Engineering Design

Shinwoong Park

*** *********** **. *** *, Blacksburg, VA 24060

469-***-****, *********.******@*****.***

EDUCATION

Virginia Polytechnic Institute and State University, Blacksburg, VA

Direct Ph.D Candidate in Electrical Engineering

Expected Grad. Date Winter 2018

Virginia Polytechnic Institute and State University, Blacksburg, VA

M.S. in Electrical Engineering

Dec 2015

University of Texas at Dallas, Richardson, TX

B.S. in Electrical Engineering, Magna Cum Laude (GPA: 3.89 / 4.0)

May 2013

Kyungpook National University, Daegu, South Korea

B.S. in Electrical Engineering (GPA: 3.88 / 4.3)

August 2013

WORK EXPERIENCE

Ph.D. candidate Research Assistant, MICS Lab, Virginia Tech

•A 3.25 GS/s 4th order Analog FIR filter design in CMOS 32nm SOI technology with split-CDAC as a coefficient Multiplier.

•Analysis and optimization on multi-section capacitive DAC

(MS-CDAC) for mixed-signal processing.

•24GHz FMCW radar system w/ 300MHz frequency modulation: Frequency divider in 8GHz Fractional-N PLL and Delta-sigma modulator + chirp input for 3-bit modulus control.

Jan, 14 - Current

Undergraduate Intern, TxACE RF & THz Lab, UTDallas

•AD

Jun, 12 - Dec, 13

Republic of Korea Navy, Jeju Island, South Korea

•Radar Operator

Jun, 05 – Aug, 07

PUBLICATIONS

1)S. Park, D. Shin, K-J. Koh and S. Raman, "A Low-Power 3.25GS/s 4th-Order Programmable Analog FIR Filter Using Split-CDAC Coefficient Multipliers for Wideband Analog Signal Processing," IEEE Journal of Solid-State Circuits(JSSC). (In preparation)

2)S. Park, K-J. Koh and S. Raman, “Analysis and Optimization of Multi-Section Capacitive DACs for Mixed-Signal Processing," IEEE Transactions on Very Large Scale Integration (VLSI) Systems. (In preparation)

3)S. Park, D. Shin, K. J. Koh and S. Raman, " A Low-Power 3.25GS/s 4th-Order Programmable Analog FIR Filter Using Split-CDAC Coefficient Multipliers for Wideband Analog Signal Processing," 2018 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2018.

4)S. Park, D. Shin, K-J. Koh and S. Raman, "A 3.25 GS/s 4-Tap analog FIR filter design with coefficient control using 6-bit split-capacitor DAC as a tunable coefficient multiplier," 2016 IEEE Dallas Circuits and Systems Conference (DCAS), Arligton, TX, 2016, pp. 1-4.

5)D. Shin, S. Park, S. Raman and K-J Koh, “A subharmonically injection-locked PLL with 130 fs RMS jitter at 24 GHz using synchronous reference pulse injection from nonlinear VCO envelope feedback,” 2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Honolulu, HI, 2017, pp. 100-103.

6)R. Xu, J-Y. Lee, D-Y. Kim, S. Park, A. Zeshan and K. K. O, "0.84-THz imaging pixel with a lock-in amplifier in CMOS," 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), San Francisco, CA, 2016, pp. 166-169.

7)D. Y. Kim, S. Park, R. Han and K. K. O, "Design and Demonstration of 820-GHz Array Using Diode-Connected NMOS Transistors in 130-nm CMOS for Active Imaging," in IEEE Transactions on Terahertz Science and Technology, vol. 6, no. 2, pp. 306-317, March 2016.

8)D. Shim, Y. Zhang, R. Han, D-Y. Kim, Y. Kim, S. Park, A, Zeshan, E-Y Seok and K. K. O., "CMOS sources and detectors for sub-millimeter wave applications," in Microwave Conference Proceedings (APMC), 2013 Asia-Pacific, vol., no., pp.512-514, 5-8 Nov. 2013

9)D-Y. Kim, S. Park, R. Han, K. K. O, “820-GHz Imaging Array Using Diode-Connected NMOS Transistors in 130-nm CMOS”, 2013 Symposia on VLSI Technology and Circuits, Kyoto, Japan, June, 2013.

RELEVANT COURSE

RFIC Designs

Phase-Locked Loops

ADV Analog IC Design

VLSI Circuit Design

Basic Semiconductor Devices

ADV Microwave & RF Eng.

TECHNICAL SKILLS

Programming Language : C, C++, Verilog HDL

Software Applications:

Cadence, ADS, MATLAB, Protel Altium Designer for PCB design, LabVIEW,

AWR Microwave Office, Origin Pro, Visual C++, Code Composer Studio, Xillinx

Hardware : MSP430 Launch Pad, Basys3 (FPGA prototyping board)

HONOR & SCHOLARSHIP

Magna Cum Laude at UTD

Fall 2011 - Spring 2012

Erik Jonsson School Scholarship at UTD

Fall 2011 - Spring 2013

Dean’s list, of Erik Jonsson School

Fall 2011, Spring 2013

Undergraduate Research Award at UTD

Fall 2012

The third Place in Senior Design I at UTD

Fall 2012

Scholarship for Academic Excellence at KNU

2009 - 2010

The second place in Creative Engineering Robot competition

Fall 2008

VISA STATUS

Green card application is in progress via wife’s citizenship. (Currently, F-1)

Contact this candidate