Engineering Project

Idamakanti Amulya

E-Mail: *********.**@*****.*** Mobile Number: +91-779*******

To work in a challenging environment that provides opportunity to learn key technology areas, and to be an asset for the organization by delivering to the best of my capabilities.

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Qualification

Year

Name of the Institution

University

%

M.Tech(VLSI&Embedded Systems)

2016

DRK Institute of Science and Technology,Hyderabad

JNTU-H

86.3

B.Tech(Electrical &Electronics Engineering)

2014

Chalapathi Institute of Engineering and Technology, Guntur.

Acharya Nagarjuna University

83.45

Intermediate

2010

NRI Academy, Guntur.

Board of Intermediate

93.60

S.S.C

2008

Sivani Public School, Ongole.

Board of Secondary Education

89.00

Languages : C,C++,Verilog,VHDL

Database : SQL.

Tools : Xilinx,Matlab

Operating System : Windows7/8 and Linux

Good inter personal communication skills and having good team spirit.

Ability to work under pressure.

Open to Learn.

Hardworking and dedication.

Attended a university level seminar on “Magnetic Induction” in RVR&JC engineering college.

Volunteered in NOVUM 2014 technical symposium.

Presented a Term paper on “Dynamic Stability Enhancement of Power System Using FUZZY LOGIC Power Stabiliser”.

Submitted B.tech Academic project- 2014 “Selective harmonic elimination in UPS using FUZZY LOGIC technique”.

Submitted M.tech Academic project-2016 “Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic”.

B.TECH Project:

# Title: Selective harmonic elimination in UPS using fuzzy logic technique.

Description:

In today’s world Uninterruptable Power Supply (UPS) plays a vital role in power failure in computers and many electronic infrastructures. UPS saves lot of work interruptions and also saves money. In this UPS due to non-linear loads, harmonics are produced. We should eliminate these harmonics for proper functioning of UPS. Thus we use a fuzzy logic technique for switching angles required to eliminate this harmonics.

M.Tech Project:

# Title: Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic

Description:

Digital multipliers are the most critical arithmetic functional units. The overall performance of these systems depends on the throughput of the multiplier.As the usage of the multiplier became

More and more its performance will decrease as its logic may not work properly, As it won’t be Economical, since Inorder to increase Multipliers performance and efficiency of working along with its usage we have an technique of using Row Bypassing,also to hold the proper logic for accurate results we use a logical circuit called “Adaptive hold logic”. Through these technical circuits we can have an reliable performance which makes an economical sense.

I.AMULYA, K.SRINIVASA RAO, “Design and implementation of Aging-Aware of Reliable Multiplier with Adaptive Hold Logic ”, ” International Journal of Research in Electronics & Communication Engineering”,Vol-4,Issue 5,sept-oct 2016.

Name : Idamakanti Amulya

Father Name : Idamakanti Bala Krishna Reddy

Gender : Female

Nationality : Indian

Date of Birth : 14thApril, 1993.

Languages Known : English, Telugu and Hindi

Address : Flat No:207, Panduranga Park view,

Bandari layout, Nizampet, Hyderabad.

I hereby declare that the information given above is true to the best of my knowledge and belief.

.

. I.Amulya.

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