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Engineer Technical

Location:
Beaverton, OR
Salary:
80 to 100K
Posted:
June 28, 2018

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Resume:

OBJECTIVE

Seeking a challenging and rewarding Technical Manufacturing Engineering position

AREAS OF EXPERTISE

Problem-Solving

Platform Hardware technologies

Mechanical engineering

Technical Leadership

Technical Innovation

PCB Fab/Assembly technologies

EDUCATION

Master of Science in Industrial Engineering (GPA 4.0) Kansas State University

Manhattan, Kansas, 1980

QUALIFICATIONS PROFILE

35 years of experience at Intel Corp. with Senior technical leadership and management positions

Excellent technical knowledge in the field of mechanical engineering design and manufacturing processes including machining, forming, and injection molding

Excellent knowledge of Printed-Circuit-Board (PCB) Fab and Assembly

Expert in the development of second-level-interconnect (SLI) technologies for BGA and LGA packages

Excellent track record in development of new platform hardware technologies related to thermal management, interconnect socket and PCB technologies

Possess a proven ability to develop and implement new innovative and world-class patented technologies to support organizational objectives

Command dynamic technical skills which motivate and direct teams to success through innovation and leadership classes

Proven ability to develop and implement the innovation program and process across 7,000 people organization

Exceptional interpersonal, communication and presentation skills

WORK EXPERIENCE

Project Manager

Virginia Garcia Memorial Health Center

Hillsboro, Oregon Aug. 2016 – March, 2018

Implemented a new Learning Management System -- “Cornerstone”

Senior Principal Engineer, Advanced Platform Technologies

Intel Corporation (Retired),

Hillsboro, Oregon

Jan. 1981 – June 24, 2016

Led “Advanced Platform Technologies” group in Systems Validation Engineering (SVE).

Developed (16) patented platform hardware technologies -- Includes thermals, PCBs and interconnect disciplines

Implemented world-class socket interconnect and thermal technologies for Intel’s packages that saved Intel tens of millions of dollars. These include high density sockets and thermal tools (2watts – 250 watts) for Devices, Client and Server market segments

Developed and implemented temperature margining tools to temperature margin processors and chipsets from -10 C to 120 C

Qualified and implemented RoHS compliant Pb-free assembly process on Intel’s Validation boards.

Developed and implemented PCB interposer technologies to expedite validation of processors, reduce TTM and launch Intel’s processors and chipsets faster saving Intel tens of millions of dollars

Innovation leader -- Developed innovation program and innovation Intel University (IU) classes and successfully implemented across Intel’s organization of over 7,000 employees

Regularly teach technical leadership pipeline classes to senior engineers to develop a strong technical organization across Intel and help engineers in their career development

LEADERSHIP

Platform Hardware Technologies

Intel Corporation

Pioneered patented electrically-transparent interconnect socket technology for validation and led teams to successful implementation

Pioneered thermal tools for validation for temperature margining and led teams for successful implementation

Developed Zero-Keep-Out (ZKO) interconnect systems for sockets and interposers to debug and validate directly on the form-factor PCBs and deployed internally within Intel and externally to OEMs.

Technology Conferences/Forums

Intel Corporation

Initiated and chaired Intel-wide (5) thermal and interconnect technology conferences attended by over 150 technical experts to share technologies and build a strong Intel technical community

Held quarterly thermal/interconnect/PCB technology forums since 2005 to share technologies within and across organizations

Held SVE-wide Innovation Day in 2013 to generate innovative ideas. Many ideas are being implemented

Held Intel-wide Platform Technologists Workshop in 2015 to understand Intel’s future challenges and developed plans to address them

Technical program co-chair of Industry-wide “Burn-in and Test Strategy” (BiTS) workshop’ 2015 and 2016.

Technical Leadership and Innovation Classes

Intel Corporation

Developed Intel University (IU) innovation class, trained 30 instructors (Train-the-Trainer) across different geos around the world and taught classes to promote innovation. This has resulted in multiple innovations at Intel.

Coached/mentored and successfully promoted (4) technical individuals to the “Principal Engineer” position

Taught (20) technical leadership pipeline IU classes for engineers of different disciplines

Technical leadership champion to build technical leadership team at Intel’s new Guadalajara, Mexico facility

PUBLICATIONS/PATENTS

Published and presented (6) papers in the field of thermals and interconnect technologies and presented at external conferences

Published and presented over (10) papers at Intel’s internal conferences

Awarded 16 US and Internationals patents in the field of Platform Hardware Technologies

Invited guest speaker at American Society of Materials and at Tyco Electronics

AWARDS

Intel Quality Award (IQA) (2009 and 2015) for demonstrating values -- Quality, Risk-taking, Discipline, Great-Place-to-work-For and Innovation

Intel Achievement Award (IAA) (2006) for developing and implementing metallized particle interconnect technology for socketing packages

(20) Intel Divisional Achievement Awards for technical innovations in the area of platforms, thermals and interconnect sockets

Suma Cum Laude, Kansas State University, 1980



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