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Electrical and Computer ENgineering

Azusa, CA
March 21, 2018

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Nikhil N. Gohil



*** *. *** ******* ***., Apt B Voice: 513-***-****

Azusa, CA 91702 USA E-mail: Education University of Cincinnati, Cincinnati, Ohio USA Advisor: Dr. Ranga Vemuri M.S., Electrical Engineering(GPA: 3.83) Graduated: November 2017 Priyadarshini Institute of Engineering and Technology, Nagpur, Maharashtra India B.E., Electronics and Communication Engineering June 2010 Professional


Intel Corporation, Folsom, California USA

Design Automation Intern - Power Estimation and Optimization Nov 2015 - Apr 2016 Ô Improved deployment time of the tool PowerArtist across the design team by validating new versions and maintaining the perl wrapper

Ô Improved design

ow by writing scripts to mine relevant data from tool logs Ô Helped front-end design team by analyzing power di erences between front-end and back-end power numbers



Physical VLSI Design

VLSI Design Automation

Low Power VLSI Design

Computer Architecture

VLSI Testing and Validation

Digital Circuits (Undergraduate Course)

Research Topic Design of DPA-Resistant Integrated Circuits Ô Tested resistance of di erent


op con gurations to di erential power analysis (DPA) attacks Ô Created a design

ow to implement DPA-resistant circuits using a custom combinational cell library and di erent


op con gurations.

Skills Languages: Perl, Verilog, Unix shell scripts, C++.

Tools: Synopsys Design Tools (Design Compiler, IC Compiler, Custom Designer, Nanosim, HSPICE, Hercules), Magic Layout Editor, IRSIM, Modelsim, Matlab. Projects


Implementation of a Channel Routing Algorithm

A C++ Implementation of the Left-Edge algorithm (with dogleg-routing) for channel routing given a netlist of connections.

Implementation of Graph Partitioning Heuristic

A C++ Implementation of the Kernighan-Lin Heuristic to partition a graph with minimum cost

(interconnections between the split partitions), given a netlist of connections. Power analysis using Synopsys utilities

Used Design Compiler and Power Compiler to analyze circuit power consumption. Further, used clock gating and Multi-voltage Design (Static Voltage Scaling) for power reduction. Scan Chain Insertion

Inserted an internal scan chain into a given design(booth multiplier). Used Synopsys DFT compiler for scan chain insertion and generated test patterns using Tetramax ATPG. Design of a 10x10 interconnect network IC

Used the layout tool MAGIC to design a custom bit-sliced 10x10 interconnect network inside a padframe. The IC was fabricated.

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