Engineer Hardware Design

Raul Herrera

**** ********* **.

Newark, CA *****

Tel 510-***-****

Cell 510-***-****

Email: **************@*******.***

Objective

Work in an Engineering organization that provides a challenging environment in which I can apply my 30+ years of design experience on R&D and allow me to grow.

Skills

● Quick to adopt and understand new technologies.

● Worked in multiple start-up companies, involving technology selection, CAD SW evaluation, lab equipment, Operations and Manufacturing support; all in addition to the Hardware Design.

● Proven experience in design, bring-up, and debugging of complex PCAs and multi-board systems, keeping DFM/DFTT rules in mind, and interfacing with various Engineering groups, including (but not limited to) PCB layout, ASIC, Software, Mechanical, Manufacturing, and System Architecture.

● Able to debug and solve complex design problems, even when the design is not my own (i.e. troubleshooting ASICs)

● Very familiar with Lab equipment such as Logic Analyzers, Oscilloscopes, TDRs, Curve Tracers, Ovens, traffic generators, Spectrum Analyzers, etc.

● Successfully designed systems that yielded positive EMC/EMI and UL test results.

● Designed complex power supply distribution schemes with a multiple voltage, high current requirements and low-level noise margins (up to 17 per PCA).

● Familiar with UNIX, windows, Linux, RTOS operating systems.

● Working experience with the following Interfaces: DDR, DDRII, DDR3, PCI, 68K, SPI4.2, SPI4.1, XAUI, JTAG, CAM, QDR, SDRAM, I2C, OC192, OC48, 10GbE, 1Gb, ATM

● Working experience with following devices: Motorola CPU’s, IBM CPU’S, Freescale CPU’s, Cavium III multicore processor, Broadcom PHY and switches, Intel PHY, Xilinx and Altera FPGAs

● Hardware CAD tools: Schematic capture (OrCad, Mentor, Viewdraw), Allegro PCB layout tools

● Firmware tools: VCS simulation environment, Xilinx, Altera, Synplify.

● Software: Python, Verilog, Corelis, JTAG, LabView.

● Database tools: Agile, Arena.

Recent

Experience

2006-2017 Santa Clara, CA

Senior Hardware Engineer

● Designed a new generation of low cost trusted IP Network to serve the South Korean Market with a box with 80 Gbps of throughput ( 40G, 4 x 10G) in a single card using a Cavium III multicore processor.

● Designed a low cost, flow base router that supports 20Gbps of throughput

● Supported the internal and external SW development teams on the implementation of the new hardware platform Software using the Cavium III multi core processor

● Support of our Korean customers. due the quality of our product we did not have a need for a large team. most of the RMA that we received were due aging on the Magnetic Hard Disk. Our ASIC, and the Hardware had very few issues.

● Brought up the next generation ASIC (“Tomahawk”) that overcame microcode and performance issues.

● Supported the local manufacturing for our chassis. Due to budget restrictions, the Hardware team had to support the Operations and Manufacturing of the systems. For example, I was the team lead on the database migration from Agile to Arena.

● Developed scripts for Manufacturing/Verification using Python, Unix scripts and Corelis JTAG tools. Modified LabView programs to support our contract manufacturing team (Jabil, in San Jose,CA).

● Designed a control card with a Freescale CPU that reduced the number of PCAs, making it possible to introduce a low cost system.

1998–2006 San Jose,CA

Senior Hardware Engineer - Team Lead

● Team Lead/Senior Designer of a family of cards (OC192, OC48, OC12, 1Gige, 10Gige, control) for a Terabit switch.

● Mentor Junior Engineers on best practices of PCB and FPGA designs, Reuse of modules, debugging, design verification, use of JTAG and overall system design. Acting manager when required.

● Worked on the design of a Flow-State router with 18 line cards in a single chassis, with an aggregate backplane Bandwidth of 240 Gbps, while maintaining carrier grade reliability.

● High speed PCB experience, up-to 10 Gig on line cards and Power distribution design with up to 9 different voltage requirements on a single PCB.

Additional

Experience Consultant. Review of design. San Jose CA ATM/Connectware R&D, Hardware Engineer Foster City, CA Syvanet R&D, Hardware Engineer San Jose, CA

R&D, Hardware Engineer Mexico City, Mexico

Consultant for a ASIC company Signal integrity Fremont, CA Education

1979-1985 EE / Acoustic . Politecnico Mexico, Mexico. 1980-1981 AS, Bakersfield College, CA.

Contact this candidate