SRIKAR REDDY NAINI

Akron, Ohio, ***** ac4urt@r.postjobfree.com Mobile: +1-330-***-****.

SUMMARY

• Career interest in Analog-Mixed/ RF signal design, Layout design, Verification and Testing.

• Experience with industry standard cadence, Spectre RF, Xilinx, Eagle CAD PCB tool

• Good knowledge in designing operational amplifiers, ADCs, DACs, Bandgap references, RF circuits, LNAs, Mixers, VCOs

• Created Floor plan and various Layout techniques for good Layout

• Ability to understand and solve the problems, work in team environments TECHNICAL SKILLS

• Circuit Design Simulators: Cadence Virtuoso, AWR MWO, Virtuoso Layout Editor, Assura and Calibre DRC and LVS, Spectre RF simulator, MATLAB, Simulink, Multisim, Eagle CAD, OrCad, Xilinx, PSpice

• Languages: C, JAVA

• Technologies: TSMC 0.35 μm, TSMC 65 nm, AMS 0.18 μm, Virtuoso 0.35 μm Hands on experience with Spectrum Analyzer, Digital Storage Oscilloscope, Power Meter, Signal Generator, Multimeter, Vector Network Analyzer.

EDUCATION

University of Akron, OH GPA: 3.8 Jan. 2016 – May. 2018 Masters in Electrical and Computer Engineering

RELATED COURSE WORK

Analog IC design, RF IC design, VLSI design, Advanced Analog IC design, ADC and DAC, Digital signal processing, Error control coding, Wireless communications.

WORK EXPERIENCE

Design Engineer at Semtronics Micro Systems June 2014 – Dec 2015 A Compact Low Power Bio-Signal Amplifier Chip: Tools used: Cadence Virtuoso, Eagle CAD (Testing)

• Design, simulation, layout and test of the low power Bio-signal amplifier with extended linear operation region which has constant gain of 46 dB with a linear operation region from 0.3 V to 3.08 V, high CMRR, low power and compact area in TSMC 0.35 μm

• Used to read the ECG signals from the body. Tested by using the sample ECG signal and shows good results Low Power Neural Amplifier, Tools used: Cadence Virtuoso

• Design, simulation of high CMMR, high PSSR and high input impedance neural amplifier in TSMC 0.18 μm. It includes Current mode Instrumentation amplifier, Offset Cancellation loop that reduces the electrode offset voltage effect. This is used to check the EEG and ECG signals from the human body Rail-to-Rail Output Buffer, Tools used: Cadence Virtuoso, Eagle CAD (Testing)

• Design, simulation, layout and test of Rail-to-Rail Output Buffer which includes a rail-to-rail differential pair combined with the output stage transistors in a negative feedback configuration. This buffer has high output swing and low output resistance. Designed in TSMC 0.18 μm

Analog- Mixed Signal Graduate Research Assistant Jan. 2016 – Present Ping-Pong Auto-Zero Amplifier Chip, Tools used: Cadence Virtuoso, Eagle CAD (Testing)

• Design, simulation, layout and test of a 4 channel Ping pong auto-zero amplifier which reduces the input offset voltage with high gain, high CMRR, high PSRR, good phase margin in AMS 0.18 μm

• PCB is designed to test the proposed amplifier in Eagle CAD. Using this test setup, oscilloscopes, signal generators, power meters and multimeters, the parameters DC offset voltage, open loop gain, CMRR, PSRR, noise, GBW, slew rate are measured

Block Modelling of Transistors

• Transistor block modelling of CMOS transistors operating in saturation region for easy and effective analysis of CMOS circuit designs i.e. analytical approach to design CMOS circuits replacing conventional complex small signal analysis with some tradeoff

• Applying and analyzing the model for several amplifiers, output stages and verifying their parameters CMOS Voltage Reference Circuit: Tools used: Cadence Virtuoso

• Design, simulation, layout and test of CMOS voltage reference circuit consisting of sub threshold MOSFET’s. It generates two voltages having opposite temperature coefficients and adds them to produce an output voltage with a near zero temperature coefficient. The temperature coefficient of the voltage was 15 ppm/OC (-20 to 80O C) and 20 ppm/V in supply voltage range from 1.4-3 V

Design of Low Noise Amplifier, Tools used: AWR MWO

• Designed a cascaded LNA with center frequency of 1.84 GHz in AWR MWO

• The design specifications are Gain >15dB, Noise figure < 1.8dB, IIP3 > -10dB, Return Loss < -10dB Design of Two Stage Low Noise Amplifier, Tools used: AWR MWO

• Designed a two-stage amplifier operating at 10 GHz frequency. Bias network is designed

• Gain of designed LNA>18dB, Noise figure<2dB with 3dB and 20dB bandwidths of 3.5 and 5.5 GHz Design of Gilbert Mixer, Tools used: AWR MWO

• Design and simulation of RF CMOS Tunable Gilbert Mixer with Wide Tuning Frequency

• The Gilbert Mixer achieves tuning frequency span of 2 GHz (1.1 – 3.1 GHz), a high conversion gain of (0.5 – 6.4 dB), a low noise figure (6.81 – 8.36 dB) and power of 9mW

Low Power 10-bit SAR ADC, Tools used: Cadence Virtuoso

• Design and simulation of low power 10 bit SAR ADC. This low power ADC can be used in image sensor arrays as well as multi-channel portable neural recording frontend systems. This design is done in TSMC 0.35 μm 10-bit Time Mode Hybrid DAC, Tools used: Cadence Virtuoso

• Design and simulation of an area efficient 10-bit time mode hybrid DAC with current settling error compensation in AMS 0.18 μm

Folded Cascode Amplifier with Gain Boosting Technique: Tools used: Cadence Virtuoso

• Design, simulation, layout and test of folded cascode amplifier with gain boosting technique to the output transistors to increase the gain. The gain is around 100 dB with good phase margin Graduate Teaching Assistant at University of Akron, OH. Jan. 2016 – Present

• Demonstration of lab experiments for basic electronic circuits

• Guided students in design of various Analog and RF circuits in Cadence design tool

• Graded student’s homework’s, exams and lab reports PUBLICATIONS AND PRESENTATIONS:

N. Srikar Reddy, K.S. Lee, “Ping-Pong Auto-Zero Amplifier with Rail-to-Rail Output Buffer” Mar 2017

N. Srikar Reddy, K.S. Lee, “Folded cascade amplifier with gain boosting technique”, Jan 2017

Poster presentation and talk on “Ping-Pong Auto-Zero Amplifier with Rail-to-Rail Output Buffer” at “NE-Ohio Regional Workshop on Community Infrastructure for Analog Circuit Design” workshop

Contact this candidate