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Assistant Engineering

Lubbock, Texas, United States
March 11, 2018

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Sri Harsha Amerneni

*** ******* *** *#***, Lubbock, TX 79415 Contact: 806-***-**** OBJECTIVE:

Actively seeking for Full-time opportunities in the field of IC Design/Validation where I can enhance my skills towards professional and organization’s growth.


Master of Science in Electrical and Computer Engineering August 2016 May 2018 (Expected) Texas Tech University, TX 79415 GPA 3.888/4

Bachelor of Technology in Electronics and Communications Engineering June 2011 May 2015 Jawaharlal Nehru Technological University, Kakinada, India. GPA 3.8/4 TECHNICAL SKILLS:

Languages (including HDLs): C, Verilog, VHDL, MATLAB, System Verilog Tools: NI LabView, CADENSE, HSPICE, Xilinx ISE Design Suite, ModelSim, NI AWR, Synopsis Design Vision, Synopsis IC Compiler. Data Analysis: JMP and Microsoft Excel

Platforms: Windows, NI Test Stand


Texas Tech University - Teaching Assistant September 2016 – PRESENT Currently Working as a Teaching Assistant for the Course Modern Digital System Design at Texas Tech University. My responsibilities include assisting undergraduate students from the Electrical and Computer Engineering Department with their classwork also conducting tutorial sessions on the Verilog Programming and help the students with their projects. Avanthi Institute of Engineering and Technology- Teaching Assistant July 2015 – June 2016 Previously worked as a Teaching Assistant for the courses VLSI Design and Embedded Systems. My role includes helping the students from the Electronics and Communication Engineering department with their mini projects in Embedded systems and conduced information sessions on the latest advancements in the field of VLSI Designing and Transistor Technologies. Also Demonstrated the laboratory safety techniques and supervised the experiments in the Circuits Lab to ensure safety of the students. ACHIEVEMENTS

• Awarded with the Best Design Project from Dr. Chagzhi Li at Texas Tech University for the Design Project of a Temperature sensor from a PTAT current generator Circuit Using 0.6μm CMOS Technology in CADENSE.

• Awarded with Seacat Scholarship from the department of Electrical and Computer Engineering at Texas Tech University for the entire grad school.

• Also Awarded with Gold Medal during my Under Graduation in Electronics and Communication Engineering from Avanthi Institute of Engineering and Technology for emerging as the topper in the batch 2011-2015. PROJECTS

• Testing of 8-bit, μP Compatible ADC0802: Performed all the basic tests to evaluate the ADC 0802 performance characteristics using the NI STS (ATE) and also on the NI PXIe 1075 and on the Bench Equipment Using Keithley 24xx, Agilent E3648A, NI Virtual Bench, MSO6054A Oscilloscope. Also, calculated the Cp, Cpk and %GRR for the obtained measurements using the JMP Software and evaluated the stability of the measurements derived from the tests. Also, evaluated the Tester to Tester Correlation for the obtained measurements between the ATE, PXIe 1075 and Bench Equipment.

• Testing of Low Power Current Output DAC0800LC: Validated datasheet by testing various parameters of DAC0800LC using SMU keithley 2400, NI Virtual bench and Agilent E3648A. Calculated the Cp, Cpk and %GRR of the obtained test measurement using JMP software. Using the LabView I have automated the Bench Equipment to perform the tests on DAC0800.

• Testing of 8-line to 1-line data Multiplexer SN74ALS151: Evaluated the performance of the multiplexer on the NI My DAQ using the LabView programming software. Data Analysis for the obtained measurement results was carried through JMP and MATLAB and calculated the Cp, Cpk and %GRR for the obtained measurements.

• Design of a Temperature Sensor from a PTAT Current Generator Circuit using 0.6μm CMOS Technology in CADENSE: Designed a Temperature sensor using PTAT Current Generator circuit on CADENSE and performed the stability analysis and drew the layout for the proposed design. The simulation results obtained from the design were 22.79 degrees of phase margin and 18450μm2 area for the layout.

• Design of Pipelined RISC CPU using Verilog HDL: Developed a modular based Verilog Model for pipelined RISC CPU. Designed modified register file, function unit and instruction decoder modules separately and designed a main module which instantiates each of these submodules in a pipeline structure.

• Design of a Pass Transistor Logic Based Full Adder and 7:3 Compressor Using 32nm CNTFET: Designed a Full Adder and and 7:3 Compressor Using 32nm CNTFET and 32nm Bulk CMOS Technology on HSPICE. Also measured the Peak Power, Delay and Power Delay Product from the Obtained simulations and performed the comparison analysis between 32nm CNTFET and 32nm Bulk CMOS.

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