TZU-YUN WENG (Debby)

Address: **** ** **** *** ********* OR 97333 Tel: 541-***-**** E-mail:ac4ra3@r.postjobfree.com

OBJECTIVE

Seeking internship, co-op experience or full-time employment as an entry level electrical engineer with superb work ethic, collective culture values, focus and determination, effective communication and problem-solving skills

EDUCATION

Oregon State University, Corvallis, Oregon, USA Expected graduation March 2018

Master of Engineering, Electrical and Computer Science

Related Coursework: Analog and digital communications, Contemporary Energy Applications,

Digital Signal Processing, Digital Circuit Design, Electrical and Magnetic Fields, Stochastic Signals and Systems, Computer Architecture, Digital Signals Processing, Semiconductors, Oversampling Delta-Sigma Data Converters, Electronic Material Processing, Application Specific Integrated Circuit Design, Circuit Analysis.

Tamkang University, Taipei, Taiwan June 2014

Bachelor of Science, Electrical Engineering

PROJECT EXPERIENCE

Designed, implemented and tested a prototype of USB powered audio amplifier: Fall term 2015

Using discrete components. Outputs at least 60dBm, Stereo output, and adjustable gain.

Total harmonic distortion less than 30%. Receives audio signal from any source through auxiliary input.

Designed an adjustable DC power supply: Winter term 2016

Each channel was able to supply at least 900mA per channel continuously, at voltages between 2 and 12.

Current limiting circuitry for each channel, protecting above 1 Amp 10% tolerance).

Voltage ripple less than 0.75Vp-p in amplitude per channel with both channels fully loaded to 900mA.

Safely equipped with a cooling fan that should not normally be running at 70 F, but should reach rated

speed around 95 F.

Power supply assembled safely and with no electrical hazards, and utilizes a safety fuse.

Design of a video bandwidth Delta-Sigma A/D Converter: Spring term 2017

The design and simulation of a 16-bit 10 MHz bandwidth analog to digital converter. The modulator is designed with an oversampling ratio of 35 using a cascade of integrators feedback (CIFB) form.

The full delta sigma modulator design includes Matlab, Simulink and Cadence simulations of the DS modulator and decimation filter.

Non-ideal effects have been investigated and their impact quantified.

WORK EXPERIENCE

McNary Dining Center, Oregon State, Corvallis OR September 2017-present

Assisted chef with variety of tasks to ensure customer food orders are prepared quickly and accurately

Effective team member with high level abilities to cooperate, collaborate and communicate with

co-workers and up to 3000 customers a day

Morning Breakfast Shop, Taipei, Taiwan August 2012-January 2014

McDonald’s, Taipei, Taiwan August 2012-January 2013

Noble Family Steak, Taipei, Taiwan March 2011-August 2012

Successful in cooperating and participating in a team and provided excellent customer service

Effective team member with high level abilities to cooperate, collaborate and communicate with

co-workers and customers and able to quickly learn food preparation and customer service

RELEVANT SKILLS

Software applications and languages: C/C++, Matlab, Simulink, LTSpice, Microsoft Office, Ubuntu Linux,

Autodesk 123D Design, Express PCB, Latex Coding, Soldering,CAD

Languages: English, Mandarin Chinese (Native), Taiwanese (Fluent)

Interests: Biking, hiking, playing piano and guitar, reading, fashion recycling

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