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Engineer Design

Location:
Cypress, Texas, United States
Posted:
March 05, 2018

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Resume:

Titus Stauffer

***** *. ******* ******

Houston, Texas 77070

ac4pah@r.postjobfree.com Cell 713-***-****

SUMMARY of SKILLS:

Hardware Design and Test (board-level)

DC Power, MOSFETs, analog & digital (including A to D & D to A), batteries, IDE and SCSI hard drives, drive arrays & RAIDs, PCI Express, PCI bridges, hot swap, video, GPIO, electromechanical, relays, SSRs, ethernet & token ring NICs, VCOs, transfer boards, cables, CPLDs, FPGAs, ASICs, high-speed board design, serializers & deserializers, servers, DDR2/3, GigE (barely), Fiber Channel (barely).

Applications & Programming

WinWord, Excel, Visio, Power Point, PageMaker, HTML. Schematic capture: Orcad, Viewdraw, and Cadence Allegro tools. Allegro layout viewer. RTL, Verilog, and AHDL (for Lattice CPLDs / Synplify & Altera / Max-Plus-2 & Quartus). Script files. Maintain web site pages using HTML.

EMPLOYMENT HISTORY:

Hewlett Packard E., Houston, Texas / OTSI Contractor Feb 2016-Aug 2016

Design Sustaining Hardware Engineer

Find, test, and qualify alternate components for use in HPE storage products. Help debug new issues concerning already-introduced products, and help test new components for both old and new designs of HPE storage products.

Hewlett Packard, Houston, Texas Jan 2011-July 2014

Design Verification Test Hardware Design Engineer

Design, document, and debug design verification test hardware, primarily focused on PCI Express, but also some USB 3.0, test hardware. Supervise layout. Write, modify, and debug Verilog source codes for high-end Altera FPGAs. Write code for using Altera Stratix 4 FPGAs, CPLDs, DDR2/3, and NOR flash parts. Use o-scopes, logic analyzers, and protocol analyzers to debug test hardware. Select components and enter into schematic support libraries. Maintain web site. Primary author and inventor for 5 patents pending. Laid off.

Hewlett Packard, Houston, Texas Nov 2004-Dec 2010

Manufacturing Verification Test Hardware Design Engineer

Design, document, and debug functional test hardware (same function and group as Compaq ’89 to ’99). Designed test blades for bladed-servers infrastructure testing, and wrote Verilog code for them. Bladed infrastructure and power-management test design, debug, and deployment. AC power distribution/management gear test and calibration test hardware design. Patent awarded for “shock and vibe” tester.

MKS Instruments, Austin, Texas May 2003-Nov 2004

Associate Engineer, Quality Engineer

Debug and repair boards that failed in the field. Organize BOMs, revise documentation. Write script files, build and repair test equipment. Gather & publish statistics, manage ISO9001 requirements (calibration etc.)

Symtx, Austin, Texas June 2002-Aug 2002Contract Engineer, AHDL Code for FPGA

Wrote AHDL code for an FPGA for a processor emulator for avionics testing. Used more than 90 % of an Altera EPF10KRI240, which is a fairly large FPGA. Was partly done debugging when all contractors were let go.

Surgient Networks, Austin, Texas Nov 2000-Jan 2002

Functional Test Engineer

Designed, built, troubleshot, and documented FBT (Functional Board Test) systems for a large content router. Worked with Verilog, Visio, Allegro layout viewer, and Cadence schematic capture. Used slightly less than 300 total bits of general-purpose I/O. Design used modular transfer boards and 8 different dipswitch-selected functions residing in one common set of Verilog programs on FPGAs, on one common test card type, saving work and money. UUT (Unit Under Test) here used Fiber Channel and Gig-Ethernet.

Compaq Computers, Houston, Texas Aug 1987 – Nov 2000

Product Design Engineer (June 1999 – Nov 2000)

Designed and tested small clusters (2 servers plus shared SCSI storage per cluster with ethernet inter-server heartbeat link). Installed Win NT plus test software, wrote script files, ran tests, and tweaked designs. Designed proto versions of circuits (included serializer and deserializer ASICs) for design concept validation, then helped with final product designs. Used Viewdraw schematic capture, Visio, and Verilog for CPLD coding. Proofread documentation for customers, conducted customer tours. Introduced new products to Mfg. Factory and Test Processes.

Functional Test Engineer (June 1989 – June 1999)

Designed circuit boards using Orcad, supervised layout. Debugged PCAs, wrote software specs & script files, generated documentation. Wrote programs for Lattice CPLDs. Designed and helped build and debug functional testers for testing brand-new PCAs for the board shop. Worked extensively with manufacturing diagnostics software and software teams. Specific types of UUTs tested included processors, I/O motherboards, network cards, drive array controllers, cache memory daughterboards, video cards, memory boards, and intelligent system monitors. Testers included comprehensive tests of analog battery circuits.

Designed circuits including CRC (Cyclical Redundancy Check) of digital data at the “pass-through” connector of video UUTs (this, along with analog circuitry designed by a co-worker, automated video testing), computer-controlled voltage margining, computer-controlled floating-reference battery simulator, I/O ports to control relays, FETs, A to D and D to A converters, simple local microprocessors, seemingly countless interconnect and adapter boards, etc. Designed approximately 150 boards, with at least 10 of them being quite complex (30 to 50 ICs). Designed large transfer boards for vacuum bed-of-nails testers.

Designed “hot sockets” for the EISA and PCI busses, which allow two things: 1) Kill UUT power in a live host, so that host (using custom test cards) can monitor battery operation during UUT-unpowered time, and 2) Swap UUTs w/o rebooting the host, saving test time (reducing the numbers of testers, operators, & other expenses). 1 PATENT AWARDED on a run-in test system using PCI-PCI bridges to test 12 PCI expansions (drive array controllers) at once; this included hot swap and SCSI-bus testing.

Product Engineer for Hard Drives (Aug 1987 – June 1989)

Isolated problems & resolved them with hard drive vendors. Found a noise susceptibility design problem, and a solution. Collected and analyzed factory fallout data. Wrote Symphony macros to import, parse, sort, and graph text files from a data collection system, thereby automating a tedious process of taking printouts and entering them into spreadsheets by hand. Adapted these programs for use by others in product engineering.

Digital Equipment, Colorado Springs, CO. 1983 – July 1987

R&D Eng, (1984 – 1987), and Mfg Eng for Hard Drive Disks, (1983 – 1984)

Troubleshot media (disk) testers and debugged the designs of other engineers, including read/write circuits.

Designed a multi-station start/stop wear tester, complete with automatic shutdown triggered by head crashes. A multiplexed-airflow particle counter detected head crashes. Collected, analyzed, and graphed data, mostly from disk testers.

Designed a system for allowing disk testers to write patterns, for the purpose of examining “bit shifting”, whereby magnetic flux transitions at the trailing end of an area with dense transitions tend to move (be crowded) towards areas of less dense transitions. This system included CRC “signature analysis” for insuring data integrity.

Education & Military Service, 1978-1983:

BSEE, USAF Academy; Cadet 1978 – 1982, Grad. 3.09 GPA (on 4.0 scale)

2nd Lieutenant, USAF. Worked on instructional aids for the USAF Academy faculty. These included modems, microprocessors, and stepper motors. Honorably discharged.



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