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Engineer Electrical Engineering

Chicago, Illinois, United States
March 04, 2018

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• • +1-312-***-****


Illinois Institute of Technology, Chicago, IL May 2018

• Master of Science Electrical Engineering (MSEE), GPA 3.5 Concentration in VLSI and microelectronics with a focus on circuit design, FPGA development, ASIC development and dataflow modelling in Verilog.

Savitribai Phule Pune University, India August 2016

•Bachelor of Engineering (B.E.) in Electronics and Telecommunication, GPA 3.8 Concentration in embedded systems with a focus on hardware development using Arduino, PIC microcontroller and 8051. Work Experience:

3D Printer Engineer at Vision 13, Aurora, IL Sep 2017 – Dec 2017

• Conceptualize, design, modify and build 3D printers using embedded systems and hardware engineering.

• Developed drone communication system using Arduino Due and programmed in Python for calibrating the drone and the 3D printer.

Hardware Engineer at Smart AG LLC, Ames, IA June 2017 – Aug 2017

• Worked on Smart NX and Smart HP concepts by engineering and building hardware for monitoring and controlling the autonomous vehicles. Installed and calibrated the hardware on the vehicles using mechanical tools.

• Developed circuits and IOT modules for the innovative technology using EAGLE and Python programming.

• Created bills of materials for circuits by researching components and testing them on the CAD tools. Projects:

• Research Project under Dr. Erdal Oruklu. Working on ASAP 7 ASU 7nm PDK in partnership with ARM. Jan 2018

• Designed a schematic of a pipeline multiplier in Quartus Prime on Altera Max 10 and generated a NIOS 2 soft processor hardware control using Qsys design tool by leveraging IP, peripherals, memory and processor. Jan 2018

• Designed a full MIPS single cycle processor in Verilog on ModelSim Aug 2017

• FinFET Transistor Characterization and Domino Logic Calculated FinFET transistor characteristics, delay and power using cadence virtuoso and HSPICE. April 2017

• Integrated clock gating and power gating design: Designed a new method of dynamic and static power reduction with a data retention circuit using virtuoso, HPICE and Verilog. April 2017

• Case Study for 32-bit Pipelined CPU design with new ALU Architecture and Computer simulation for digital logic. Studied and completed the logical synthesis and physical synthesis using cadence virtuoso. Sep 2016

• Worked with Cadence Virtuoso to create layout design and schematic design of various adders and inverter. Along with that studied formal verification and hierarchal design, gate and delay power and ASIC Design flow. Sep 2016

• Designed a Digitally Controlled PWM Inverter for Photo Voltaic Solar Energy. Implemented full H Bridge inverter using MOSFET to convert DC to AC and sensor circuits to sense the input and output voltage from the inverter and an algorithm for MOSFET switching. Aug 2015

• Hyperloop Pod Competition 2018: Electrical and Controls dept. Nov 2017 Certifications & Technical Skills:

• Python programming on ‘Codecademy’.

• VLSI in Python on ‘OpenBookProjects’.

• Certified and passed a C and C++ course at ‘Seed Infotech’.

• Digital Circuit design, FPGA, ASIC, Static Timing Analysis, Physical design, RTL design and transistor level schematics.

• Hardware description languages: Verilog, System Verilog, VHDL

• Tools: Cadence Virtuoso, HSPICE, Microwind, Photoshop, Linux and Shell scripting, Multisim, Arduino, EAGLE, Proteus, PSPICE and Python

Leadership & Extra-Curricular:

• IEEE, IIT Chapter, Project Chair.

• Eta Kappa Nu, IIT Chapter, Member.

•Active member of Digital Design Club, Food Science Club, UNICEF, TedX and Indian Student Org.

•Manager of a family owned restaurant.

• Won second place out of ten in IEEE Robotics Competition.

• Won the IIT Doubles and Inter Club Badminton Tournament.

• Passed Intermediate and Elementary Drawing Competition.

• Traveller, Hiker and Adventurer.

• Languages: English, Hindi, Marathi, Spanish.

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