Engineer Project

SATISH KUMAR BASAVAPPA

*********@*****.*** Ph: +1-512-***-****

Profile Description:

Over 15 years of experience in Verification, Assertion-based Verification, Formal Verification.

Experienced in IP and SoC verification, including ARM-processor based with AHB/AXI buses.

Experience in developing test plans, reviewing verification plans for completeness, coverage driven verification and driving team for verification completeness.

Experience in developing various tb components.

Proficient programmer, good knowledge in Verilog, System Verilog, UVM, C/C++ programming.

Extensive experience in Simulation tools (MTI, NCV, VCS), Assertion-based Verification & Formal Verification, Clock Domain Crossing Checks, Low-Power Verification.

Extensive experience in evaluating and deploying CAD tools/methodology.

Extensive experience in interacting with the EDA tool vendors during the evaluation and as part of methodology development.

Good written and verbal communication skills.

Work Experience :

1. Member Technical Staff, 2013 - present AMD Inc

● Leading a small team for unit level verification of Infinity Fabric

● Worked on developing and enhancing TB for IP verification for various projects

● Responsibilities include developing & reviewing test plans, developing various TB components, project planning and ensuring the IP meets the required quality metrics for the various projects.

2. Principal Engineer, 2011 to 2013 Qlogic.

● Primary responsibilities are block-level verification for Buffer Manager, RegBlk, IOHub and SPI using UVM.

● Explore new methodologies for faster functional verification closure 3. Verification Lead, 2004 to 2010, Qualcomm Inc

● Primary responsibilities are leading the SoC verification (full-chip).

● Responsibilities include project & resource planning, identifying the risks to the project, coming up with the mitigation plan, driving the test plans and ensuring the use of coverage metrics & appropriate methodologies to ensure the success of the project.

● Involved in full-chip environment bring-up, test plan creation, review of the team members verification plan to ensure completeness, driving closure of various verification tasks

(including coverage closure), vector support and post-silicon debug. 2

● Worked on block-level verification of interconnect.

● Worked extensively on bus/integration (AXI/AHB) verification and processor based verification including native tests (C/ASM).

● Evaluated & worked on Low-power verification solutions for SoCs.

● Evaluated & worked on Formal Property Checking tools, Linters, CDC tools. 4. Member Technical Staff: 2001 to 2004 Sun Microsystems, Inc., Sunnyvale, CA

● Worked as part of the Design Verification methodology team.

● Worked extensively on Formal Property Checking and deploying the property checking and ABV methodology.

● Deployed and consulted with various projects for Assertion-based Verification, Coverage driven verification and Formal Verification tools. Education:

B.Tech (Computer Science & Engineering) - Jawaharlal Nehru Technological University College of Engineering - 1998

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