Shweta Agarwal

Email: ac4ks5@r.postjobfree.com Phone: 650-***-****

Summary

Talented and passionate hardware engineer is looking for opportunities to leverage her technical experience and project management education to become a seasoned project manager. Besides my solution finding approach, I have always been appreciated for my strategic planning and delivering under tight deadlines. To get formally trained, I am about to finish my certification in Project & Program management. I am working towards my PMP certification as well. To keep myself updated with the latest trends in the Software Industry, I have recently taken some software courses as well.

Technical Skills

Product Tools: MS Word, MS Excel, MS PowerPoint, MS Project, Risky Project

Tracking Tools: Jira, Fogbugz, Bugzilla

Protocols: TCP, IP, UDP, Ethernet, Tunneling protocols, Application level protocols

Programming Languages: UVM, System Verilog, Verilog, C/C++, Perl

Developer Tools: Synopsys (VCS), Quartus, Cadence (NC Verilog, Verilog-XL, Virtuoso), Mentor Graphics (Model Sim), Xilinx ISE, Debussy

Network Analysis & Simulation tools: Wireshark, Tcpdump

Management Skills

Creating PRDs, business cases, project plans, functional and technical requirement documents

Leadership and effective negotiations

Stakeholder management

Risk assessment and mitigation planning

Project tracking, control, and reporting

Resource management and process improvement

Cross-team collaboration & strategic communication

Education

Certificate Program in Project & Program Management, University of California, Santa Cruz, Silicon Valley Extension – Aug 2017 – Present

Coursework excelled:

Management courses

-Project Leadership and Communications

-Project Integration and Risk Management

-Role of Project Management

-Managing Software Projects

-Effective Negotiations: Principles, Techniques and Strategies

-Agile Project Management Using Scrum

Software courses

-Big Data: Overview, Tools and Use Cases – Cloud computing, Hadoop

-Artificial Intelligence, Machine Learning and the Deep Learning – Introduction

Currently working towards PMP certification

Master of Science Electrical Engineering, San Jose State University

Bachelor of Engineering Electronics and Power Engineering, Priyadarshini College of Engineering & Architecture, Nagpur University, India

Work Experience

1.Intel, San Jose, CA

SoC Design Engineer – Apr 2016 – July 2017

I created a complete UVM based test bench environment from scratch for Stratix 10 products verification and added complete test suites based on the feature lists and requirements for different release phases.

I prepared status tracking and scheduling documents with coverage numbers for internal and external stakeholders.

Being a senior designer, I also created dashboard to reflect project schedule/progress, milestone reviews, issue updates across releases.

2.VSS Monitoring, Sunnyvale, CA

Verification Engineer – Mar 2013 – July 2015

I created various test benches using System Verilog and UVM. I also created test plans focusing on coverage and strategy for testing.

I mentored new college grads and actively participated in the hiring process to hire senior engineers to create a strong team for high quality releases under tight schedules.

I also worked on the side with the Product Management team and created a PRD, roadmap, business model and go-to market strategy for a new product line based on deep packet analysis for data monitoring and network analysis. The complete product release was divided into 4 phases based on mid and long-term business opportunities.

I was frequently involved in technical discussions with the Product and Sales teams to design and implement business solutions for new customers.

3.Nethra Imaging, Santa Clara, CA

ASIC Verification Engineer - Feb 2010 – June 2011

I worked at block level and full chip level verification covering all aspects of verification from RTL level to the gate level for the company’s image processing products.

I did market research on commercially available sensors for image processing and created a PRD for a generic sensor model that would be the starting point of the image processing pipeline. I then designed the sensor model in System Verilog and C++.

I worked with the chief architects, designers, software and firmware groups to get the ASIC delivered on time.

4.Cortina Systems, Sunnyvale, CA

Member of Technical Staff - May 2006 - Jan 2008

I verified the data path for various products used for Switching and Routing using Verilog at block and full chip level.

I created and modified test benches, test plans, and test cases for traffic management, bridging and switching products for the complete ASIC.

I verified the packet forwarding, learning, aging, policing, shaping and all other L2 – L3 level features in simulations and on FPGA for the pre-Si phase.

5.San Jose State University

Graduate Assistant and Verilog Lab In-Charge - Sep 2005 – Dec 2005

I mentored and guided graduate students from varied industrial backgrounds and technical skills, reviewed and provided suggestions on their grad projects.

I conducted periodic teaching sessions for Verilog.

Work Authorization

US Citizen - Authorized to work for any employer.

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