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Engineer Electrical Engineering

Rocklin, California, United States
February 18, 2018

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****, ****** **** ****. 916-***-****

Rocklin, CA 95765 Email:


Seeking a challenging position as Software Architect, Project Management, Software QA, Product Management, Technology Sales or Marketing, which utilizes my analytical skills and experience to manage or develop high quality products to contribute to overall success for the company.


8+ years of software development experience using C and Object-oriented programming for various embedded devices(ARM/Intel) in a high technology environment.

10+ years for feature, functionality, stress and performance testing for solutions to help align network devices and application resources with the priorities of the business, optimizing performance and reducing operational costs in the process.

US citizen, requires no work authorization within US.

MS. and BS. in Electrical Engineering from US accredited University


Programming: C, C++ (Object Oriented Programming), Intel x86, ARM CPU/architecture.

Embedded Chipset: Intel Wi-Fi(IOSF/discrete), Broadcom Wi-Fi(BCM432291), Gemalto 3G radio + GPS.

Scripting: Python, Perl, Shell scripting, MS DOS Batch.

Source code Repository: GIT, CVS

Web automation using descriptive language such as QTP/UFT, Selenium using chrome driver.

Web frontend technology, HTML, XML, XPATH, DOM, AWS and Web driver.

Networking protocols such as TCP, UDP, IP, HTTP(S), DNS, ARP, DHCP, SNMP.

SDLC methodology such as Agile and waterfall methodology.

Layer II switching technology such as Spanning Tree Protocol (STP), VLAN and rate limiting.

Leadership role, trained other QA Engineers and others.

Great trouble shooting and bug duplicating skills as well as test execution.

Knowledge of QA process, regression testing including test case/ test matrix, test plan creation, test script execution and bug tracking mechanism such as Jira, Bugzilla, Vantive.

Expert knowledge of IP headers, packet analyzer and packet generation tools such as Sniffer, Wireshark, tcpdump, NetXray, tcpreplay and Smartbits.

Creating secure, isolated test networking environment for all engineers.

Strong commitment to meet high quality standard for the products, good communication skills.

Willingness to learn new technology, experience working in fast paced environments.

Software: Maestro/LLVM compiler(Linux), Real View (ARM compiler), Microsoft Visual Studio, GIT, Wireshark, HP QTP/UFT, HP OpenView, Jama, Jira, SharePoint, CVS.

OS: Linux, Solaris, Windows OS(Win10/7/XP/2K), Verix V(POS terminal).


Intel Inc, Folsom, CA Mar’2017 – Present

Lead Debug Engineer, Solid-State Device (SSD NAND, IOSF Wi-Fi chipset)

SSD is top revenue generation units at Intel and growing. Responsibilities include

Debug and isolate root cause for Jira issues for Solid State NAND devices. Identify and duplicate firmware issues or enable Python scripts fixes for code review in test automation.

Content test development in object oriented programming(OOPs) for onboard Intel IOSF and discrete Wi-Fi chipset to validate driver level functionalities such as firmware upload, transmit (TxB) and receive (RxB) buffer for various commands, register access, Flow Handler(FH), INTA/Msi/Msi-x Interrupts using HOST and CSME Clink mode. Content development using LLVM(Maestro) compiler to ensure driver functionality in RTL simulation and post silicon phases. Various groups within Intel global team use these tests for validation during chipset development life cycle, therefore reducing development cost cycle per group

VeriFone Inc, Rocklin, CA Mar’2006 – Oct’2016

Sr. QA Engineer, OS Development Group

VeriFone Inc, is the global leader in Payment Terminal System. VeriFone, Rocklin office is responsible for developing Verix OS for Point of Sales(POS) terminals. Responsibilities include

Test application development for ARM based new hardware board using various embedded devices such as 802.11 Wi-Fi (2.4/5 Ghz), Touchscreen, Global Positioning System(GPS), 3G & 2G radio, Ethernet, Magnetic Stripe Reader, Contactless card, Smartcard, Bluetooth communication and printer.

Development and execution to release high quality Hardware/POS terminal to market.

Automation using Python, Perl, and XML

Packeteer Inc, Cupertino, CA 2004 – Mar’2006

Sr. QA Engineer, Development Group

Packeteer Inc, is the pioneer and global leader in WAN Application Traffic and Bandwidth Management and QOS (Quality of Service).

Responsibilities include feature testing for solutions to help align network and application resources with the priorities of the business, optimizing performance, reducing operational costs in the process using Class and Policy Management.

Vernier Networks, Mountain View, CA 2004 – 2004

Sr. QA Engineer, Development Group

Vernier Networks offers scalable solutions that manage and secure enterprise-class, mission-critical 802.11 wireless networks.

Responsibility includes feature testing of security, encryption, and authentication for WLAN Gateway system. Maintain and enhance test automation harness for daily nightly Build.

Skystream Networks, Sunnyvale, CA 2002 – 2004

Sr. QA Engineer, Development Group

Responsibility includes feature verification and stress test of Edge Media Router. The EMR is used at receiver end of Satellite link.

Feature test involving RIP routing protocol, Multicast Protocol such as DVMRP, IGMP, VLAN, STP, Satellite broadcast transmission protocols such as DVB-MPE, MPEG2, frequency modulation QPSK and BPSK and PID filtering.

Automated performance throughput analysis program using Smartbit Library and Visual Basic.

Honored Best QA Lead role.

SpeedEra Networks, Santa Clara, CA 2001 – 2002

QA Engineer, Development Group

Test validation of Web Cache servers for static Web contents. Requires clear understanding of HTTP/S, IP, ICMP, TCP, UDP and DNS packet formats.

Complex SQL Query to Oracle relational database for Web contents. Used for customer billing at Network Operations Center(NOC).

SUN MICROSYSTEMS, INC, Menlo Park, CA 1999 - 2001

Member of Technical Staff, Desktop Software Group (DTSW)

Responsibility includes qualifying network sub-systems of new platform using desktop software (Solaris 2.7) and test tools. The test involves driver installation, configuration, stressing and as well as, measuring throughput performance of platform Ultra-80.

The devices include NIC card such as Gigabit, ATM 622,100/10 Ethernet. Used the following test software, TTCP, FTP, NITS, Perf, Laddis, Data Corrupt, Netperf, Netpipe, and Nettest.

Developed Tcl scripts along with Smartbit programming library to generate mixed mode packets, packets with CRC error for positive and negative testing.

NORTEL NETWORKS (BAY NETWORKS), Santa Clara, CA 1997 - 1999

Staff Test Engineer

Responsibility includes testing embedded Agent software and system test of Bay devices.

Ensured Agent SNMP MIB functionalities including read/write specifications.

Ensured that the devices were SNMP manageable using HP OpenView and Optivity.


Systems and Integration Engineer, Open Systems Group.

Responsibility includes presale customer support, resolving technical issues on TCP/IP Protocols and applications. The configuration issues involved setting up multi-protocol support such as Novell IPX, NetBEUI or LAN Manager along with IP on Ethernet/Tokenring/Arcnet environment.

VALCOM/NETSYS INC., San Jose, CA 1991 - 1993

Technical Support Engineer

Provided pre-sales and post sales technical support to our valued customers via telephone.

Performed system level diagnostic on AT compatible desktop computers.

OKLAHOMA STATE UNIVERSITY, Stillwater, OK 1990 - 1990

Para-professional, University Computer Center

Monitor IBM 3090, VAX/VMS 8350 (ULTRIX) routine job and assist students with programs.


M.S., Electrical Engineering, Oklahoma State University, OK, USA (GPA 3.63/4.0)

B.S., Electrical Engineering, Oklahoma State University, OK, USA.


Member, Eta Kappa Nu


U.S. Citizen.


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