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Engineer Design

Onondaga County, New York, United States
February 15, 2018

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Phil Dilmore

**** ******* ******

Jamesville, NY 13078-9647

Phone: 315-***-****



Twenty plus years design experience in digital design including ASICs, FPGAs, and PCBs.

Software development for embedded DSP and for test tools.

Strong integration and debugging skills.

Project leadership including architecture development, leading cross functional teams, managing sub-contractor technical development, coordinating integration activities.

CAS from the Lockheed Martin School of Engineering Management.

Scheduling and tracking, CAM EVM certified.

Proposal experience including both technical and cost.

Strong written and oral communications skills. Windows, and MS Office, Visio, Project.

Proficient in VHDL, Verilog & C. Competent in MATLAB, C++, Assembly Code & DOORS

Clearance: Secret 2006-2013, SSBI 1995-1996, Top Secret 1997-1998.

US Patent 7457459 for Monochrome and Color Transfer.


Lead Engineer Chentronics, LLC From: Oct-13

Flame Safety Systems Norwich, NY To: Present

Lead engineer for iScan2/3 Flame Scanner. Develop TMS320 DSP based hardware and software to detect presence of flame for safety critical operation of industrial burners. Research and development of DSP algorithms to evaluate optical data.

Use Mentor Graphics PADS board development tool set and TI Code Composer Studio for software development.

Secure and maintain product approvals from FM (Factory Mutual), UL (Underwriters Laboratory), BSI (British Standards Institute) and INMETRO (Brazilian regulatory agency) regulating agencies.

Develop ATE (automated test equipment) using LabWindows C based programming to verify product functionality and support research and development.

Support production at off-site vendors. Coordinate product enhancements for producibility.

Senior Research SRC (Syracuse Research Corporation) From: Aug-10

Engineer North Syracuse, NY To: Aug-13

Hardware Lead for LCMR radar. Resolve complex technical issues in support of production. Take active role in developing hardware to mitigate obsolescence. Port existing VHDL onto new hardware incorporating enhancements. Simulate using Active HDL. Implement FPGA designs using Synplicity and Xilinx ISE. Perform system integration and validation.

Sub-array beamformer design lead for OWL program. Lead multi-discipline team developing state of sub-assembly for experimental radar system. Designed PCB with Ethernet Switch and critical timing signal distribution. Designed digital portion of RF beamformer PCB. Schematic capture using Dx Designer.

Developed flexible BIT architecture for widely used ECM hardware. Testing includes off-line invasive tests and on-line tests. Performance of communications paths, environmental conditions and VSWR checks.

Phil Dilmore

2928 Michael Ave

Jamesville, NY 13078-9647

Phone: 315-***-****


Lead Hardware Lockheed Martin – MS2 From: May-07

Engineer Syracuse, NY To: Aug-10

Integrated Product Team Lead for LCCA OBE Canister. Lead multi-disciplinary multi-site team that developed data concentrator to converted 15 data sources into single 10 Gig Ethernet optical link. Had complete design responsibility including architecture, overseeing schedule, risk management, budget, EV reporting, integration, and formal design sell off.

As Lead Hardware Engineer ensure engineering processes are followed, participated in design concept and cost estimating in support of new business, created and presented Cost Sign-off packages for Equipment Engineering, using GRID coordinate staff with functional managers.

As the Lead Hardware Engineer and Lead Digital Engineer in the Acoustic Sensors group have participated in proposals for MFTA, RAP/VLA and LCCA. Played a instrumental role in both Tech and Cost Volumes on LCCA. Played significant role in developing the IMS and EV planning, track progress as well as risks and opportunities in ROADS for MFTA.

Lead effort to drive the LAB/LVA Network Interface Card validation and integration effort. Identified needed resources, coordinated multiple disciplines, set team priorities and lent a hand developing STE sync card.

Senior Design Lockheed Martin – MS2 From: Oct-04

Engineer Syracuse, NY To: May-07

As the Lead Digital Engineer in the Acoustic Sensors group have participated in proposals for LVA, SAES, S80 OBE and NextGen TB-34 in the capacity of technical, cost, schedule and risk assessment. Have developed and tracked detailed project schedules. Schedule work assignments for four digital engineers and provide By the Name Plan input for future needs.

For the LCCA program, developed a parameterizable and flexible architecture for the Network Interface Card. With a goal of multiple re-use, this architecture supports current telemetry interfaces as well as future Ethernet implementations. Architected GigE Optical interface for use on LAB and LVA using an embedded PowerPC in a Xilinx FPGA. Have assisted several additional programs, such as ARTIST, by developing blocks of VHDL code and assisted less experienced digital engineers with VHDL and board design needs.

Architected, Coded and Verified the FPGA for the RADAR Controller Interface in the AHE Transmitter. Wrote VHDL Code and self checking testbench also in VHDL, for easy regression testing, to simulate design in ModelSim. Design features include Serial FPDP, message partitioning and building, UART interface, several I2C interface sensors and PMFL features including safety requirements. Participated in Design Verification Testing.

Designed synchronization source for a SONAR in an Altera FPGA on a PCI COTs board.

ASIC Design Hewlett-Packard - Imaging and Printing From: Feb-01

Engineer Boise, ID To: Apr-04

As part of a team, developed two generations of a pipelined image processing ASIC with an embedded ARM processor for MFP (multi-functional products, printer/scanner/fax) products. The first generation was 133 MHz with 2.7 million gates and the second was 167 MHz with 6 million gates. Worked on design from conceptual stage through proto-type verification.

Wrote HDL in Verilog, modified existing VHDL code, and synthesized in Design Analyzer. Blocks designed include front-end interface with pipeline pacing circuitry, embedded LUTs, DSP interface, horizontal and vertical scaling, and updates to existing LSB and PCI designs.

Validated design in Modelsim using VERA and Seamless tools. Used PERL for scripts.

US Patent 7457459 for Monochrome and Color Transfer in a Multi-Function Product.

Phil Dilmore

2928 Michael Ave

Jamesville, NY 13078-9647

Phone: 315-***-****


ASIC/FPGA Avnet - Design Services From: Feb-98

Engineer Rochester, NY To: Feb-01

Designed and verified a synthesizable VHDL IP Core for the CAN Bus Interface.

Performed VHDL and Verilog logic designs of up to 125MHz per customer specs in Xilinx Spartan and Virtex FPGAs. Used Synplicity and FPGA Express for synthesis and Xilinx Foundation for place and route. Validated designs with Verilog test benches using ModelSim.

Converted ASICs to FPGAs, multiple FPGAs to single device, Altera FPGAs to Xilinx.

Verified ASIC timing with Primetime and functional equivalence with Formality.

Senior Design Harris - RF Communications From: Jun-96

Engineer Rochester, NY To: Feb-98

Designed and integrated crypto communication products using Motorola 68331, PC860.

Digital logic design in 4000 Series Xilinx FPGAs using M1 Software.

Analog design including power supply, A to D, D to A, and linear circuits.

Senior Design Lockheed Martin/Martin Marietta1 - Astronautics From: Jan-95

Engineer Denver, CO To: Jun-96

Developed sub-system digital interface and control architecture.

Designed digital PC boards using programmable logic.

FPGA/ASIC design using Visual HDL (VHDL based tool).

Design Martin Marietta1 – O.R. &S.S. From: May-93

Engineer Syracuse, NY To: Jan-95

Designed digital and mixed signal PC boards with Mentor Graphics schematic capture tools.

Simulated circuits with Verilog simulations.

Experience with high speed CMOS logic, memory, interface, Actel FPGAs, PLDs, and DACs.

In a factory following role, work closely with test engineering and manufacturing to resolve production problems due to design/manufacturing errors.

Design Motorola 680XX microcode using Micro-Tech tool set.

Develop PMFL requirements for optical communication network hardware.

Note 1: In 1995 accepted an offer to transfer from Syracuse to Denver.

In 1996 Lockheed and Martin Marietta merged to form Lockheed Martin.


C.A.S. University of Colorado Completed: Dec-02

Boulder, CO GPA: 3.8

Area of Concentration: Lockheed Martin Engineering Management Program with emphasis on Management of Research & Development.

M.S.E.E. University of Colorado Completed: Dec-97

Boulder, CO GPA: 3.4

Area of Concentration: Computer Architecture, VLSI Design, Logic Synthesis, GPS, Cryptography, and Communications Theory.

B.S.E.E. Syracuse University Completed: May-93 Syracuse, NY GPA: 3.1

Area of Concentration: Sequential Logic, VHDL Design, and Communication

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