ac4how@r.postjobfree.com RAVI TEJA 618-***-**** https://linkedin.com/in/ravi-teja-11124a9b

SUMMARY

To obtain a career in Electrical Hardware Industry as a Physical Design Engineer/ASIC Design Engineer, where I can contribute my skills for organization's success and improving my technical ability while being resourceful, innovative and flexible.

Experience in RTL Design, Synthesis, Simulation and Physical Design flow.

Good communication skills and work as a team player.

EDUCATION

Master of Science in Electrical Engineering April 2017

Wright State University, Dayton, Ohio

Bachelor of Technology in Electrical and Communications Engineering April 2015

Jawaharlal Nehru Technological University, Hyderabad, Telangana, India

SKILLS

Programming Languages: Verilog, VHDL, C, C++, Java, Perl, TCL.

CAD Tools: Virtuoso, RTL Compiler, Encounter, Innovus, Design Compiler, IC Compiler, Primetime, Modelsim, Calibre, Redhawk, Xilinx ISE, Tetramax.

Operating System: Linux, Mac OS, Windows.

EXPERIENCE:

Physical Design Engineer Apr’14-Apr’15, First Pass Semiconductors

Block level Floor planning, Power planning, DeCap Insertion, Placement driven Synthesis, Postplacement timing closure, Clock Tree Synthesis, Clock Wiring, Post clock Timing Closure, clock skew fixing, late mode and Early Mode Optimization, Timing Driven and SI Driven Routing, Post Routing Timing Fixing, Fixing DRCs.

Basically, the block is timing and congestion critical. Floorplan has become a major thing for better QOR. Performed so many floorplan experiments to arrive at a better floorplan. Criticality faced while meeting the clock latency and clearing the DRC/LVS violations in metal layer ECO stage.

The design included 12 corners for functional and DFT modes. Rectilinear floorplan with lots of congestion and utilization of around 80%. Timing closure cross different corners with signoff tools.

PROJECTS

Sign-off of the Verilog code provided by cadence

Produced layouts that functioned at +2GHz clock frequencies using timing driven RTL-to-GDSII flow. Performed floorplan based synthesis of partition logic from RTL, guiding tool to create a netlist that minimized power, route congestion, and area while still achieving timing closure.

Implemented floorplan using best known algorithms and followed by portioning keeping in mind equal number of modules on each partition. Guided layout tool to create a placement that minimized routing problems and met timing, power and other required constraints. Built clock trees using standard tools and verified that trees created meet constraints for delay, slope, and skew.

Performing Static Timing Analysis using Synopsys tool Nano Time and fixing reported violations. Generating timing.lib models and analyzing them.

16-Point Complex Fast Fourier Transform

In this project 16-point radix-2 FFT were designed in structural architecture using VHDL. These designs were first simulated using the cadence simulator and then synthesized using the cadence RTL Behavior Synthesis tool. This synthesized design was simulated to check if synthesized design passes the test bench.

Finally, the design was mapped down to layout using the cadence RTL Compiler and cadence Encounter tool. This post placed routed layout was simulated to check the timing constraints &PDA product was determined.

Implementation of Fiduccia-Mattheyses circuit partitioning using C++

Implemented a circuit bi-partitioning algorithm using C++ to minimize the cut-set between the partitions while maintaining a desired balance between the size of two partitions

Doubly linked list data structure was used in the implementation. Gdb was used in the debugging process. An average of 73% cut set reduction was obtained while tested on standard golem benchmarks with consists of 150,000 standard gates.

Standard cell Library

Developed the schematics and layouts of various cells for different drive strength using Custom Designer(SYNOPSYS) for 32nm.

Simulated basic gates and analyzed the waveforms in wave viewer and seen a that all the layouts have clean LVS and DRC.

2-Way set associative Cache Design

The entire design consisted of SRAM array, Decoders, Dynamic Comparators, Sense Amplifiers, Mux’s, Hit/Miss logic etc. Cadence with 32nm PDK was used for circuit design and layout. Hspice was used for simulations at each stage of the design. Four Corner models were used for the simulation to save time. Nano time was used for the Static Timing Analysis. Hercules for DRC and LVS and StarRC for parasitic extraction. Area and power were in consideration throughout the design.

Design of a full custom microprocessor using hardware and software components

Designed a full custom 5 stage pipelined processor in Cadence-Schematic and Layout.

Major optimization in terms of area, power and delay were achieved by various techniques like dynamic logic, power gating, clock gating, Flip Flop optimization and careful sizing.

Perl was used to automate the entire flow and solve the dependencies. Back end Perl scripting was done to verify the results.

APTG for 16-bit ALU

Automatic Test Pattern Generation(APTG) for 16-bit ALU using Synopsys Tetramax. Developed VHDL and Verilog codes for 16-bit ALU and used it to find stuck-at-faults, undetected faults and fault coverage in design.

Iterative Logic Array multiple time frame methods are used for sequential generation and Synopsys Tetramax used to find test patterns of ILA multiple time frame method.

COURSE WORK:

VLSI Design Synthesis and Optimization (EE7530).

Digital Integrated Circuit Design with PLDs and FPGAs (EE6620).

VLSI Testing and Design for Testability (EE7540).

Very Large Scale Integrated Circuit Design(EE6540).

CMOS Mixed Signal IC Design (EE7580).

Mixed Signal Tools (EE8000).

Fundamentals of EE (EE6800).

Applied Linear Technique’s (EE7010).

Independent Study in Multi Carrier Waveform Technique’s For 5G (EE7900).

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