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Design Engineer Professional Experience

Austin, Texas, United States
February 09, 2018

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Tarun Arora

**** ******** **,****,******,TX 480.***.****

Summary: Experienced Ambitious Analog/RF IC Designer looking for more challenges with 5 years of working experience; Hands on Experience on circuit designing, simulations, Layout floor planning,Signal Integrity, Tape Outs, Lab measurements(Silicon testing),Smith Charts,NF,OIP3,IIP3,HD2,HD3 etc. PROFESSIONAL EXPERIENCE

Analog Mixed Signal Design Engineer, Intel, Austin Tx [March2016-Current] Low Dropout Regulator [1.2V, 22nm CMOS Si]

Fixed Input voltage .6,LDO output 1V with output variation of less then 1.5%. Phase Locked Loop [1V, 22nm CMOS Si]

I’m helping the designer who is owning the PLL in doing some simulations and testing it in the lab and the analysis for charge pump /LC tank.

It’s a LC Pll with fixed frequency range 4.8Ghz and consuming 5mA of current.

PLL has Switch capacitor based Iref generation for Chargepump and VCO. Lab Measurements and Simulations

Hands on Experience on taking the measurements and simulations for LDO,BG, PLL .

Performed the task of automating the various Instruments for Measurements. MTS Analog Design Engineer, R2 Semiconductors, Sunnyvale CA [Feb2016-March2016] I/o Pads Buffers for SPMI and I2C Bus [1.8V,TSMC .18 um]

TX capacitive feedback topology with fixed slew rate over all PVT and load variation from 10pF to 100pF for SPMI and open drain topology for I2C with VOL less then 20% of VDD for load variation from 10pF to 550pF

RX-Schmitt trigger with glitch filter for glitches of 50ns and 10ns on the clock for I2C and switching threshold of .7*VDD to VDD and 0.1*VDD to .4*VDD with hysteresis of .3*VDD. Analog IC Design Engineer, Sabertek Inc., Irvine CA [Sept 2013- Jan2016] Digital Highly linear Variable Gain Amplifier Full chip (Fully Differential VGA) [5V, 0.36um BICMOS SiGe]

Responsible for whole chip; Baseband Signal 3dB BW up to 10MHz for base stations applications.

Differential BICMOS Op-Amp consists of class AB output.

Gain can be varied from 0dB to 40dB as minimum and maximum gain respectively with gain steps of .5dB.

Chip had very challenging specs like High OIP3, IP3, High Swing I/p and O/p common Mode, Low power and Low Noise.

Performed HB Simulations for OIP3, IIP3; other simulations were performed for output NOISE, NF, STB, AC. ETC.

Executed the floor planning for all the sub-blocks to the top level .Post layout simulations were performed and analyzed the problems of Electro migration, IR drop, parasitic analysis etc. Low Dropout Regulator [1.4V, 65nm CMOS Si]

Designed for on chip and off chip cap for lower and higher current rating 1mA~100mA and drop out voltage of 200mV.

Modified the circuit tricks to maintain good supply rejection even at high frequencies -20dB till 10MHz and -60dB at Dc

Circuit was simulated for Noise, Load regulation, Line regulation supply rejection, PM and transients for various cases.

Executed the floor planning of all the sub-block to the top level. Multiple Bandgap Circuits (Voltage References) [5V, 0.36um, 1.2V-65nm]

Optimized the Bandgaps for 360nm CMOS and 65nm CMOS.with variation of less than 2mV VerilogA behavioral models

Worked on Biquad filters both in Laplace blocks and RC configurations, TIA both in Laplace and RC configurations ACADEMIC EXPERIENCE

Low Noise Amplifier – [1.2V, 65nm CMOS]

Worked on differential low noise amplifier using cascoded CS inductive degeneration topology at the frequency of 2.2GHz, achieved 120MHz bandwidth, 20dB gain, 2.66dB noise figure, S11, S22 of -9.5dB and power consumption of 7.4mW in 65nm CMOS process technology

Course Work

Analog IC Design,Advanced Analog IC Design,ADC (Delta Sigma) (Audited),RFIC Design(Audited),High Speed I/O,VLSIDesign,Advanced VLSI Design(SRAM Design)


Design Tools Cadence (Spice/ HpsiceD, Virtuoso/Caliber(DRC/LVS), Spectre),Xilinx ISE 12.1 Lab Instruments DMM,Digital OscilloScope,Analog/Rf Function generators,Clock Genrators,Temperature Controllers,Spectrum Analyzers

Programming Languages C, C++,Perl, Verilog /Verilog A, MATLAB, Ocean Scripts Operating Systems Linux/Unix, MS-DOS, MAC OS, Windows (XP, 7, Vista). EDUCATION

Arizona State University,


MSE specialized in Analog and Mixed Signal Design. Graduated –May 2013 Kurukshetra University, India. Bachelors, Instrumentation and control Engineering. Graduated –June 2010

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